Cadence has talked about System Design Enablement for the last few years, taking a more holistic view of designing a system. This means taking into account not just the chip(s) in the system, but also the packages, boards, and the software load that runs on the SoCs. If an SoC is being designed in a leading edge node (say 7nm right now) then there is a lot of focus on chip design and the new issues at that node (such as whether EUV is being used or not). This makes it easy to miss the importance of other changes that are going on, such as the almost universal use of emulation and FPGA prototyping to get software developed and tested in parallel with everything else. The biggest concern outside the chip is...well, everything in the rest of the system, especially if it is big and complicated. There is sometimes a view that small, simple systems don't have any problems in this area. But the small systems often have to live with cost constraints that more complex systems do not have (such as coarse routing, and no blind vias). And often they have radios, which are always a challenge at the board level. For example, in my post The $10 Rasperry Pi Zero , Roger Thornton (of the Raspberry Pi Foundation) described his constraints: A six-layer board sounds like quite a lot but the top of the board is all components, so there is no room for routing. There are two internal power planes since the radios, in particular, need a good power delivery network. So there were two signal layers left. The track and gap width kept cost down but lost a lot of "space" just due to the size of the traces. Being restricted to drilled vias had two issues. The vias are relatively large. And every via requires space on every layer. There are a lot of traces, too, since there are two SDIO buses, four GPIO, HDMI, USB, CSI, and all the control signals. Another unusual requirement was aesthetic: since Raspberry Pi sells bare PCBs, they need to look good, too. OK, most of us don't have to worry too much about making our circuit board beautiful. But another flavor of design of increasing importance is the so-called "More-than-Moore" designs, with multiple die in a single package,. Often, these are very high performance, meaning that advanced signal integrity analysis is required. Over the last decade or two, chips have gone from using more and more pins as a way to get signals out of the chip, to using fewer pins but with very high-speed SerDes interfaces running at 16GBps, 56Gbps, with more than 100Gbps on the horizon. Obviously, this creates a huge challenge to design the SerDes transmitters and receivers, but it also has a huge impact on the package and board design. This particular problem has led to the whole AMI modeling infrastructure. For more on that, see my post AMI and IBIS: Who Put the Eye in AMI? Next generation designs using DDR5 DRAM will require these techniques too. Going up to really big systems, like cloud servers, or 5G base stations, brings a further complication. For a chip on a PCB, the design is close enough to two-dimensional that the third dimension is a second-order effect. But once you have multiple boards, or flexible boards, and backplanes, then the third dimension becomes important (I know this sounds a bit like the opening of The Twilight Zone ). Furthermore, signals don't just magically cross from one board to another, there are connectors, cables, sockets, and more. Traditionally, the way this type of thing was analyzed was to create a separate model for each piece of interconnect and then cascade these models together in a circuit simulation tool. This can be an error-prone process, especially for the highest speed designs where the transition from the connector to the PCB or the socket to the PCB needs to be optimized. Sigrity 3D At CDNLive Japan today, Tom Beckley gave the Cadence keynote. He announced the Sigrity 2018 release, which enables designers to take a holistic view of their system (well, not really including the software, to be honest) extending design and analysis beyond the package and a single board, to include connectors and cables. An integrated 3D design and 3D analysis environment allow PCB design teams to optimize the high-speed interconnect of PCBs and packages in the Sigrity tool and automatically implement the optimized PCB and IC interconnect in the appropriate members of the Allegro family: Allegro PCB, Allegro Package Designers, or Allegro SiP Layout, without the need to redraw. This automates what has traditionally been a tricky manual process (aka error-prone). But it also saves days of design cycle time by eliminating re-drawing and re-editing. In the limit, this can save hundreds of thousands of dollars by reducing prototype iterations and re-spins. 3D Workbench A new 3D Workbench utility available with the Sigrity 2018 release bridges the mechanical components and the electronic design of PCB and IC packages, allowing connectors, cables, sockets and the PCB breakout to be modeled as one with no double counting of any of the routing on the board. Interconnect models are divided at a point where the signals are more 2D in nature and predictable. By allowing 3D extraction to be performed only when needed and fast, accurate 2D hybrid-solver extraction to be performed on the remaining structures before all the interconnect models are stitched back together, full end-to-end channel analysis can be performed efficiently and accurately of signals crossing multiple boards. When appropriate, the simulation results can be validated against industry standard compliance requirements. With the upcoming DDR5 and the intermediate DDR4X standards requiring AMI, this is an area which will only get more important. For more details on this, see my post AMI for DDR5 Made Easy . In addition, the release offers rigid-flex support for field solvers such as the Sigrity PowerSI technology, enabling robust analysis of high-speed signals that pass from rigid PCB materials to flexible materials. Design teams developing rigid-flex designs can now use the same techniques previously used only on rigid PCB designs, creating continuity in analysis practices while PCB manufacturing and material processes continue to evolve. Summary Reduce risk and save days of design cycle time with unique 3D design and analysis environment Automate high-speed interconnect of PCBs and IC packages without redrawing Perform full end-to-end channel analysis efficiently and accurately of signals crossing multiple boards Bridge the gap between mechanical and electronic domains with the new 3D Workbench utility Perform analysis of high-speed signals that pass from rigid PCB materials to flexible materials Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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