Today, it is TSMC's 2018 Open Innovation Platform (OIP) Ecosystem Forum in the Santa Clara Convention Center. TSMC has two big events each year (in the US, they also take them on the road to other countries) and almost every major announcement gets made at one or other of these two events. Today, the big announcement is TSMC's cloud-based design environment for both digital and custom design, which goes under the name TSMC OIP VDE (which is incredibly long if you spell out all the acronyms in full). This was created in partnership with Cadence, Amazon Web Services (AWS), Microsoft Azure, and others. I think it is clear that cloud-based design, such as Cadence Cloud and now TSMC's VDE, is the biggest trend in design starting with this year. See my post Cadence Cloud for details of our original announcement at DAC, or my post CDNLive Japan: 対応ポートフォリオ for a description of running a cloud-based library characterization job in the cloud in front of a live audience on a Japanese AWS datacenter. If you just read the press releases, you will be a bit confused as to how this works in practice. Is there a Cadence Cloud? And a TSMC Cloud? How do you pick which one to use? So I called up TSMC's Suk Lee to get some more color. The storefront is handled by Cadence, so if you are a design group who wants to use this, then you come to Cadence. Obviously, we supply the design tools. But you are also allowed to upload whatever TSMC collateral you are authorized to use, such as PDKs and design rule files. In effect, TSMC is embracing the cloud through what Suk called "a one-stop shopping model". Cadence will basically take care of everything, including the cost of the cloud, the tools, access to TSMC collateral, and so on. Suk told me that there are really three key messages about VDE: First, there is the certification from a security point of view, to make sure that the cloud is secure to the degree that TSMC are comfortable having their collateral in the cloud. There is no restriction on which nodes are supported—you can do a 5nm design in the cloud, not just non-leading-edge processes. Security is a big issue with design groups, not just TSMC, so they can piggy-back on this security work and sleep soundly. Second, there is the heavy duty design process that you want to do in the cloud. It turned out that this required more pipe-cleaning than expected. The press release describes the process in more detail: Microsoft and Cadence collaborated with SiFive, a TSMC IP Alliance partner, to tape out the first full SoC design in TSMC’s OIP VDE. It contained its 64-bit multi-core RISC-V CPU, the Freedom Unleashed 540, which is capable of running a RISC-V Linux distribution and its applications via TSMC OIP VDE. The SiFive implementation was done in the U.S. and India. Thirdly, there is the creation of the Cloud Alliance, of which Cadence is an inaugural member. Another less obvious aspect of this is that there is a do-it-yourself model, where you can mix and match with tools from any of those Cloud Alliance members. The Cloud Alliance, by the way, consists of both cloud vendors, and tool vendors, what you need to get the design infrastructure in place. There is a lot of certification around! Cadence holds a Microsoft Partner designation and is an Advanced Technology Partner in the AWS Partner Network (APN) and has achieved AWS Industrial Software Competency status. By aligning the TSMC OIP VDE with the Cadence Cloud-Hosted Design Solution, mutual customers benefit from improved productivity, scalability, security and flexibility through scalable compute resources available in minutes or hours instead of months or weeks, achieving better overall throughput in the development process. I have to say that if I was starting a fabless semiconductor company today, I would not consider building up compute infrastructure, I would go straight to the cloud. Obviously, big companies already have huge server farms in place and they are not going on the scrap heap. But when they need to get expanded or upgraded, I think that going to a hybrid solution is the next step. Cloud-only doesn't seem so extreme when Netflix runs their entire business in the cloud (and on one of their biggest competitor's infrastructure, as it happens). As I said above, for more details on Cadence Cloud, see my post Cadence Cloud . There are also some posts on specific aspects such as simulation (see Simulation in the Cloud) , library characterization (see Liberate Trio: Characterization Suite in the Cloud ), and no-human-in-the-loop design flows (see Deep Learning and the Cloud ). It is safe to predict that I will be writing more posts about Cadence Cloud in the months to come. 7nm+ and 5nm At the TSMC Technology Symposium in May, I said: This isn't the biggest surprise announcement of the year. Cadence is collaborating with TSMC on 5nm and 7nm+ high-performance processes primarily targeted at advanced mobile and high-performance computing (HPC). There is certification of the digital and signoff flow, the custom/analog flow, and the library characterization flow. There is a press release, but you can pretty much take last year's, or the year before's, and just lower the numbers. The entire Cadence tool portfolio supports the entire TSMC process portfolio. Well, even less surprisingly, that collaboration continues Cadence: today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs. As part of the collaboration, the Cadence digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC 5nm and 7nm+ processes, and the corresponding process design kits (PDKs) are now available for download. Customers using Cadence’s implementation, signoff and custom/analog tools are already in production with 7nm+ projects, and there are multiple design projects underway with early 5nm customers. There is more detail on the precise tools certified in the press release, but basically, the digital flow, analog flow, and library characterization flows are supported in the way you would expect. Both 5nm and 7nm+ involve some EUV layers. I expect that during OIP, TSMC will present a more detailed roadmap on 5nm and 7nm+ availability, and probably some hints about what comes next. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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