The talk of the town in the DRAM market (well, apart from its growth in the last couple of years) is DDR5. You might assume from the talk that JEDEC has finalized the standard, but it is actually technically still in development. I believe that the final standard is still expected before the end of the year. At TSMC's OIP Ecosystem Forum, Cadence's Marc Greenberg and Micron's Ryan Baxter presented on DDR5 Challenges and Solutions . The two companies decided not to wait for the final ink to dry on the standard since engineering takes too long, so they agreed on a detailed spec that was close to what they expected the final standard to be. Cadence developed DDR5 interface IP and Micron developed a DDR5 DRAM prototype. When all the silicon came back and was working (within 3 days!), I wrote a post in May DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s . The other motivation for the joint project, in addition to just getting started, is that interoperability is the only real way to prove standards compliance. You can see that it is all working from the data eye in the diagram to the top left which is at 4400 Mbps. The big drivers for the DDR3 and DDR4 transitions were driven by client and mobile. But the big driver for DDR5 is the need for bandwidth. Servers require greater memory bandwidth since system memory bandwidth is not keeping pace with server CPU core count growth. That sentence actually contains a lot of nuances. Memory bandwidth is not being driven by processor speed increases requiring corresponding memory bandwidth increases, that game finished many years ago. instead, silicon real-estate is being used to add more cores per chip. DRAM scaling has been getting more challenging from a density point of view, leading to a mismatch. The chart on the right shows this graphically, with the line at the bottom showing bandwidth per core (basically unchanging)), the yellow line showing CPU core count, and the dark blue line showing system memory bandwidth. Earlier in the year, Marc explained it to me: As memory die get bigger, they get slower, due to all sorts of laws of physics. As you start building a 16Gb die in 1X memory technology, the distances start to get really long, which changes a lot of core timing parameters for the worse. Then the memory can't keep up with the CPU and so has to be overdesigned, making it bigger still, and so on. But everyone wants more memory in each server, for bigger datasets, bigger databases, bigger designs, The speed of the core is unchanged, but the I/O is higher speed. The table above shows the expected adoption trends for DDR5 (including LPDDR5) in the three main markets: server, PCs, consumer/industrial devices (I think mobile is in here). The process node column is the node for SoCs incorporating DDR5 IP. Memory technology has its own roadmap and naming conventions. The chart on the right shows the breakdown in the market with the bright red DDR5 growing in the middle, and LPDDR5 in maroon(?) at the top, with the two of them growing to over 1/3 of the market. DDR5 is not just a faster implementation of what has gone before, it has: increased data rates improved command bus efficiency increased bank group for improved performance improved refresh schemes scalable beyond 16Gb monolithic density 2 independent 40-bit channels per module Just taking everything except the speed increase, comparing DDR4 3200 vs DDR5 3200, there is already an increase in bandwidth of 1.36X. Add in the speedup and comparing DDR4 3200 to DDR5 4800, there is a 1.87X increase (is that close enough for a marketing guy to say 2X?). Ryan said that 16Gb production device will be late next year, manufactured at a sub 18nm process node. DDR5 allows for future scaling, but when DRAM manufacture reaches 10-12nm it will need a lot of help, since it will require the die to do a lot more than before (variable retention time, and other atomic level phenomena). Marc came back to say that Cadence has 7nm and 7nm+ designs using the IP starting, and will go to more advanced technologies in the future. So far it is all server and client, but consumer and industrial will be along later. The summary: DDR5 has revolutionary performance benefits. In 2022, everyone will use it. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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