While many attendees of the Design Automation Conference focus on the exhibits, DAC continues to have a top-notch technical program as well. At DAC 2014 June 1-5, Cadence will play a key role in the technical program by participating in a dozen panel discussions and 15 paper sessions. That's in addition to one breakfast panel and three lunch panels, as described in a recent blog post.
Following is a list of panels, paper sessions, and workshops with Cadence participation. That means that each event listed here has Cadence authors, panelists, presenters, or organizers. This list does not include the technology sessions that will be given at the Cadence booth (#2616) or the customer/partner presentations at the Cadence Theater. For further information about Cadence activities at DAC 2014, see our DAC microsite.
Panel Discussions
Monday, June 2
- 10:30am-12:00pm: What Large IP Companies Want. Room 105
- 11:30am-12:15pm: Giga-Scale Design Challenges: Billions and Billions of Transistors. Pavilion Panel
- 1:30pm-2:15pm: China Fabless - Threat or Opportunity? Pavilion Panel
- 1:30pm-2:30pm: Cooley's DAC Troublemaker Panel. Room 236/238
Tuesday, June 3
- 1:30pm-2:30pm: Beyond 14nm - Which Fork in the Road? Room 306
- 3:45pm-4:30pm: Who Drives Whom? High-Level Synthesis or IP Reuse? Pavilion Panel
Wednesday, June 4
- 1:00pm-2:15pm: Building, Verifying and Deploying Internet of Things...a Practical Analysis. Room 252/254/256
- 1:30pm-2:30pm: FinFET and IC Design - Mountain or Mole Hill? Room 306
- 2:30pm-3:15pm: Design Walkthrough - An Advanced Driver-Assist System for High-End Cars. Pavilion Panel
- 4:00pm-6:00pm: System Engineering Methods and Tools for Automotive EE Design. Old Wine in a New Bottle? Room 310
Thursday, June 5
- 3:30pm-5:30pm: Designing In Security. What Will It Take? Room 309
- 3:30pm-5:00pm: HW/SW Co-Design for Computer Vision. Can We Make Computers See? Room 306
Technical Paper Sessions
Monday, June 2
- 10:30am: The Modern IP Factory - IP Development for High Quality. IP Track, Room 101
- 10:30am: High-Speed Top-Down Design from Architecture to RTL. Room 307
- 1:30pm: The Virtual Chip - Validating and Emulating End-to-End System Performance. IP Track, Room 101
- 1:30pm: High-Performance WIFI AFEs. IP Track, Room 105
- 4:30pm: Power-Ware Macro Modeling Techniques. IP Track, Room 101
- 4:30pm: High-Level Synthesis IP Modeling for Memory Controller Designs. IP Track, Room 105
Tuesday, June 3
- 10:30am: A 3D DFT Demonstrator. Room 105
- 1:30pm: The Concurrent Model Interface for the Parallel Simulation of Loosely Synchronized Many-Processor Platforms. Room 101
- 4:00pm: Exhaustive Formal Verification of Sequentially Deep Data-Transport Components. Room 105
Wednesday, June 4
- 10:30am: Going Where No HLS Has Gone Before. Room 300
- 12:00pm: Assessing the Accuracy of Layout-Dependent Effect Flow in 20nm and 14nm. Poster session, Room 100
- 1:30pm: Advanced Profiling and Optimization of UVM-Based Verification Environments. Room 101
- 4:00pm: ePlace Electrostatics Based Placement using Nesterov's Method. Room 303
Thursday, June 5
- 1:30pm: Anti-Aging Secrets for Chips. Room 307
- 3:30pm: C-Mine: Data Mining of Logic Common Cases for Low-Power Synthesis of Better-Than-Worst-Case Designs. Room 307
DAC Workshops
- Sunday, 8:30am-5:30pm: Suite of Embedded Applications and Kernels
- Sunday, 1:00pm-5:00pm: Multi-Processor Platforms for Low-Power Real-Time Embedded Applications
See you at DAC 2014! And be sure to see our Multimedia Site for live blogging and photos and videos from DAC.
Richard Goering
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