It almost goes without saying: One of the toughest challenges in implementing processor cores is striking that delicate -- sometimes contentious -- balance between performance and power. With that balance in mind, ARM this week (Sept. 24) rolled the latest in its ARM Cortex-M series of processor cores, the ARM Cortex-M7. The 32-bit device doubles the compute and digital signal processing (DSP) capability of existing (and powerful) ARM-based MCUs while keeping power under control. Using a Cadence implementation flow, design teams can wring even more power optimization from the ARM Cortex-M7 and tackle tough parasitic extraction issues along the way. We'll post about that in detail next week during ARM TechCon . For now, here's a peek at the ARM Cortex-M7 ( table below, courtesy ARM ), which sits atop the spectrum of ARM Cortex processors ( see chart, right ) starting with M0 (lowest cost and area) and running up through the M4 (a digital signal control processor with DSP accelerated SIMD floating point capabilities): ISA Support ARMv7-M DSP Extensions Single-cycle 16/32-bit MAC Single-cycle dual 16-bit MAC 8/16-bit SIMD arithmetic Hardware divide (2-12 cycles) Floating Point Unit Single- and double-precision floating point unit IEEE 754-compliant Pipeline 6-stage superscalar + branch prediction Performance Efficiency 5.04 CoreMark/MHz* Performance Efficiency 2.14 / 2.55 / 3.23 DMIPS/MHz** Interconnect 64-bit AMBA4 AXI, AHB peripheral port (64MB to 512MB) Instruction Cache 0 to 64KB, 2-way associative with optional ECC Data Cache 0 to 64KB, 4-way associative with optional ECC Instruction TCM 0 to 16MB with optional ECC Data TCM 0 to 16MB with optional ECC Memory Protection Optional 8- or 16-region MPU with sub-regions and background region Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts Interrupt Priority Levels 8 to 256 priority levels Wake-Up Interrupt Controller Up to 240 wake-up interrupts Sleep Modes Integrated WFI and WFE instructions and sleep on exit capability Sleep and deep sleep signals Optional retention mode with ARM Power Management Kit Bit Manipulation Integrated instructions and bit banding Debug Optional JTAG and ports. Up to 8 breakpoints and 4 watchpoints. Trace Optional instruction and data trace (ETM), data trace (DWT), and instrumentation trace (ITM) Targeting Market applications for the ARM Cortex-M7 processor include next-generation vehicles, connected devices, and smart homes and factories. Companies including Atmel, Freescale, and ST Microelectronics are counted among early licensees. The rollout comes 10 years after ARM introduced its ARM Cortex-M family just as the world of system design began moving more and more toward mobile solutions that were both power- and size-constrained. And mobile is still picking up steam: During those 10 years, more than 8 billion cores have shipped, more than half of them in the past 18 months, according to Thomas Ensergueix, ARM senior product marketing manager. More information about the new processor is available at ARM . Next week at ARM TechCon, Cadence's Paddy Mamtora, Product Engineering Group Director, Digital and Signoff Business Unit, will join with ARM Principal Engineer Aditya Bedi Wednesday (Oct. 1) at 4 p.m. to talk about pushing the boundaries of embedded design with ARM Cortex-M processors. Brian Fuller Related Stories : -- Cadence at ARM TechCon 2014-High Performance, Low Power, Mixed Signal, and More -- Cadence events at ARM TechCon 2014![]()
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