If you want to know what’s going on in the world of semiconductor memory, there’s no better place to be than MemCon 2014 , which takes place Wednesday, Oct. 15, in Santa Clara, California. MemCon is the memory industry’s premier technical and ecosystem event, and it offers valuable insights for anyone working with memory, systems integration, IP development, semiconductor design, and system on chip (SoC) development. And you can’t beat the price—it’s free. MemCon was organized by Denali Software for nine years through 2010, the year that Cadence acquired Denali. After a brief hiatus, MemCon had a very successful return in 2012. MemCon 2013 was a one-day conference that included keynotes, a panel, and technical tracks (see blog listing at end of this post). MemCon 2013 drew large audiences for keynotes and technical presentations. MemCon 2014 is also a one-day conference. The morning session begins at 9:00am and includes these keynotes: Follow the Data— Chris Rowen, Cadence Extending the Life of the World’s Most Successful Memories— Farhad Tabrizi, Samsung Trends in Mobile Application Processors— Mike Demler, Linley Group The afternoon session includes four tracks, as follows: TRACK 1: Mobility Invesas – A 128-bit DDR3L Memory Module Using QFD and BVA Cadence – DRAM Scaling Challenges and Solutions in LPDDR4 Context SK Hynix – Wide I/O 2 – The Revolutionary Memory Solution to Achieve High Bandwidth and Low Power Tektronix – Techniques for Validation and Debugging of LPDDR4 Memory Designs Uniquify – DDR System Analyzer – A New Way to Explore and Characterize DDR System Margins TRACK 2: Infrastructure/Networking Samsung – Understanding DDR4 and Today’s DRAM Frontier MoSys – Memories for Extreme Networking Xilinx – High Performance DDR4 Interfaces with FPGA Flexibility SK Hynix – High Bandwidth Memory – Memory Solution for High Performance Processors Synopsys – Reliability, Availability, and Serviceability (RAS) for DDR DRAM Interfaces TRACK 3: Emerging Technologies EDA2ASIC Consulting – Tackling the Memory Wall with 2.5D and 3D ICs Tezzaron Semiconductor -- DiRAM4: The High Performance Computing Extreme Networking RAM NetSpeed – Achieving End-to-End QoS Cadence – LPDDR4 – It Is Not Just for Mobile Anymore Altera – Memory Use Cases in FPGA-Enabled Systems TRACK 4: System Design and Ecosystem Keysight Technologies – Debug and Validation Techniques for DDR4 and LPDDR4 2400 and Beyond TSMC – Next Generation SoCs Memory Requirements – Embedded and Interface Solutions Future Plus Systems – Performance Measurements That Can Improve Latency and Bandwidth of Your DDR4 System eSilicon – 2.5D, How to Reduce Power, Cost and Complexity to Accelerate Market Adoption Technical sessions run from 1:00pm to 5:35pm, and will be followed by a cocktail reception in the exhibit hall at the Santa Clara Conventions Center. Seating is limited, so register now! Meanwhile, keynote, panel, and session proceedings from MemCon 2013 are available online. Richard Goering Blog Posts About MemCon 2013 - Wide I/O 2, Hybrid Memory Cube (HMC) – Memory Models Advance 3D-IC Standards - MemCon Samsung Keynote: New DRAM and Flash Memory Architectures are Needed - MemCon 2013—Keynote, Panel, and Session Proceedings Available - Semiconductor Memory Challenges Will Be Overcome, MemCon Keynoter Says - MemCon Panel: Promises and Pitfalls of 3D-IC Memory Standards![]()
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