Many electronic design teams would like to use the same models for virtual platforms (or “virtual prototypes”) and high-level synthesis (HLS). It’s possible but challenging, and some new standards are needed, according to panelists at the IEEE-SA (Standards Association) Symposium on EDA and IP Interoperability Oct. 6, 2014. Sponsored by Cadence, Synopsys, and Mentor Graphics, the one-day symposium took place at Cadence headquarters in San Jose, California. The panel was titled “ Making Virtual Platforms Real” and was moderated by Shishpal Rawat, chair of the Accellera Systems Initiative . Panelists were as follows, shown left to right in the photo below: Mike Meredith , solutions architect for system-level design, Cadence Bryan Bowyer , senior product marketing manager for HLS, Calypto Johannes Stahl , software development and architectural design, Synopsys Trevor Wieman , principal engineer in Pre-Silicon Solutions Group at Intel Because both virtual platforms and HLS use SystemC models, engineers have naturally wondered whether common models can be used for both. Virtual platforms, however, are primarily aimed at software development, requiring models that are extremely fast. HLS does hardware implementation, and demands models that are more accurate. Here’s what the panelists had to say in their opening statements about virtual platforms and HLS. Mike Meredith – Different Methodologies There are many reasons why design teams would like to use common models, according to Meredith. By using the same model for software development and hardware implementation, designers could be assured that the model they’re writing software for actually matches the functionality that will be on the chip. Further, fewer models means less effort and fewer bugs due to differences between models. “One model stays in synch with itself better than two models stay in synch with each other,” he said. However, virtual platform and HLS models have different characteristics. One is the different level of granularity in communications. For example, a virtual platform model for an image processor might pass a million-pixel frame as a single transaction, while a model for HLS might only transfer one pixel – or perhaps 100 pixels -- at a time. The good news, Meredith said, is that techniques exist for using common models for virtual platforms and HLS, and people are doing it. “The bad news is that there is no broadly accepted methodology, and different users are doing it in different ways,” he said. One technique is to encapsulate interfaces in sockets, and allow API calls into the sockets. You can then have two model implementations – one that uses the API to communicate, and another that uses wires and protocols. Bryan Bowyer – Standards are Needed Bowyer noted that virtual platforms are expensive and difficult to build. Many companies that use HLS have built their own virtual platforms and have not used SystemC, resulting in a “fragile non-standard system.” Later on, it’s too difficult to rework the platform. “What we really need is a standard, and what better to drive a standard than synthesis?” he asked. So what’s needed? A synthesizable SystemC standard (under development now), a standard transaction level, a standard transaction library, functional coverage in SystemC, and most of all, more customer participation. “We could revolutionize how hardware design is done, and bring everyone up to this new abstraction level that is really suitable for HLS and virtual platforms, but there needs to be some driver to bring it together,” he said. Johannes Stahl – A Variety of Platforms Stahl defined virtual prototype as “an early simulation model at a high enough abstraction level to enable architectural design and software development.” However, he noted, a virtual platform could be many things – an algorithm, an instruction set simulator, an interconnect or memory subsystem model, or anything “high enough and fast enough” for useful work. Stahl noted that Synopsys published a book detailing 12 case studies of virtual platforms. He asked the audience, how many do you think used HLS? An audience member quickly guessed the answer – none. Stahl said, however, that he suspected that many HLS users have developed their own virtual platforms. Trevor Wieman – Worlds Apart HLS and virtual platforms “are in the same universe but are worlds apart,” Wieman said. Virtual platform users are “squeezing every cycle out of simulation that they can” to run fast simulations, while HLS users need to describe the hardware accurately enough to run synthesis. If you’re modeling a counter for high-level synthesis, you might decrement the counter at every clock edge. For a virtual platform, you would determine when the counter will time out and just schedule that. The speed difference could be 1000X or more. “We need a more holistic perspective on what to do with standards,” Wieman suggested. Two potential areas for standardization are configuration parameters and registers. In both cases HLS needs a lot more detail than virtual platforms. “Our holy grail,” Wieman said, “is a single model serving both high-level synthesis and virtual platforms.” Questions and Answers Q: Many companies have pre-existing HDL. Is there a tool to convert HDL back to C models in order to get a simulation speedup? Bowyer : Unless they are changing the abstraction level in the model, they are not really speeding simulation. Meredith: Structurally, an RTL model has a specific granularity of abstraction. One thing you do in virtual platforms is to expand the size of the data that is presented to the model. You can’t do that if you start from an already completed implementation. Q: Is there a way to add incrementally more information to a SystemC model? Meredith: As a rule, I think that starting with virtual platform code and attempting to turn that into an HLS model is not the best approach. If you build an HLS model, you do some things to change the granularity of the transactions and to increase the speed. If you come the other way you never quite get to something synthesizable. Q: Where does FPGA prototyping come in? Does it solve some of the speed issue and maybe take you up to 200MHz? Stahl: The biggest usage for FPGA prototyping is when you want to connect something to the real world. You can connect an FPGA to the real world and do some real validation. Q: Should we make SystemVerilog a subset of SystemC? Bowyer: SystemVerilog does not have the same memory infrastructure that we have in C++. The stuff we do with template specification, in particular, is well above anything we have in SystemVerilog. Bringing that into the SystemVerilog flow makes sense, but at the moment SystemC is a shorter path. Wieman: I think the languages are very powerful together independently. Putting them together might create a mess. I would say leave them separate, and couple them together when needed. Richard Goering Related Blog Posts Archived Webinar – An Introduction to High-Level Synthesis DAC 2014: High-Level Synthesis (HLS) Users Share Advantages, Challenges Sean Dart Q&A: Former Forte CEO Discusses Past, Present, and Future of High-Level Synthesis![]()
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