On March 18, Cadence and ARM announced a groundbreaking deal that provides reciprocal access to relevant IP portfolios from the Cadence IP Group and ARM. The agreement grants both companies rights to manufacture test chips containing Cadence IP and ARM IP and to provide development platforms to customers. I sat down with Martin Lund, Senior Vice President of Cadence’s IP Group, to talk about the deal. Q: What’s this agreement all about? Lund: We’re announcing an agreement that allows engineering teams at ARM and Cadence to put together and test out interoperability of our IP. It’s a fantastic agreement. This agreement will allow ARM IP and Cadence IP to be pre-verified so customers can get to market faster with less trouble. Q: So it covers IP from both companies? Lund: It covers ARM IP and all Cadence interface and verification IP. Q: A big part of this agreement is to ensure IP is pre-verified. How do Cadence’s VIP technologies fit into this? Lund: Cadence’s broad VIP portfolio enables availability of higher quality IP earlier, a key differentiator that was already being leveraged in the Cadence IP development process and enjoyed by Cadence IP customers. Unique technologies such as TripleCheck, broad availability of SoC protocols, maturity of ARM’s AMBA protocol VIPs and support of the latest memory standards mitigate the IP-level protocol compliance risks in SoC integration. Having IP blocks pre-verified by Cadence’s VIP solution also gives customers the ability to construct their SoC testbenches based on development platforms provided (by Cadence or ARM). All this enables customers to focus on their own key differentiators and get to market faster with less trouble. Q: The benefits of this agreement sound like they will go a long way toward boosting engineering productivity in terms of IP use and integration. But there are pieces of SoC integration verification that this doesn’t cover, right? Lund: While the risks of protocol conformance level concerns are largely mitigated with this collaboration, a customer’s unique product differentiation in SoC architecture, software integration, and functional performance still needs to be verified. Cadence VIP used for IP verification also provides a basis for the development environment that customers can use to leverage existing, or create new, scenarios targeted to verify this unique SoC functionality. Q: So talk to us about the “trouble” you just mentioned. What kind of design engineering issues does this agreement address? Lund: What goes into making an SoC today? Engineering teams can create IP cores internally or they can buy the cores from third-party vendors like Cadence, like a DDR interface or a memory controller. And then they go and get processors from ARM and perhaps some system IP as well. Now you have your building blocks—your Legos, if you will—and you have to put them together. Putting it together is a lot of work, and a lot of that work is around verification. You want to make sure all those building-block pieces fit together. Now, unlike Legos, third-party IP and various IP cores don’t just snap together. For example, during initial IP integration, SoC teams spend lots of time and effort integrating interfaces, optimizing signaling, connectivity, and configuration. They then spend even more effort on integration verification. We’re taking a lot of trouble out of that equation. We’re also giving engineering teams more peace of mind that they’re not going to find some incompatibility late in the design process that can torpedo their SoC schedule. Q: So I’m a team lead responsible for IP integration and I have cores coming in from Cadence and ARM. Now I don’t have to worry about verifying them quite as much? Lund: Sure. Now, it’s never going to be like “just add water.” Building SoCs and chips is an incredibly complex undertaking that requires expertise. But, with this agreement, a lot of that trouble can be taken away because we already have done that integration. You’ll be picking cores that already have been integrated. Or maybe we have built a test chip so it’s seen silicon and it’s proven out. In addition, it’s not just about silicon. There’s also the software piece, right? If you have software, the software will be proven out on top of the ARM IP and the Cadence IP, so you know that you can probably leverage a lot of that work and reduce the effort in building chips and getting to market faster. Q: That’s huge risk mitigation. Lund: It is huge. There are two aspects to that risk mitigation. One is “what if I find something late in the design process?” The other thing is it’s also effort mitigation. Consider the effort that you otherwise would have spent putting these pieces together and working out issues. You can now spend that time wringing out the last bugs from the system. You can spend more time on the system architecture than you otherwise would have had. Q: I can’t recall an IP deal of this magnitude and scope before, can you? Lund: To our knowledge, it’s the first time such a broad interoperability agreement between two IP vendors has been put in place. You’re taking one of the leading processor companies in the world and putting it together with Cadence, one of the world’s leading interface and memory IP vendors, and together we are committing ourselves deeply to our customers’ success. Q: We announced a deal with ARM last year, but that was about tools, correct? Lund: The deal that was announced last year allowed Cadence tools—digital and verification tools—to use the ARM IP and get optimized scripts and flows around that and to really add value on top of the ARM IP. This is different. Here, we are giving IP cores to ARM and they’re giving us access to IP to build cores around ARM IP and support the ARM ecosystem. It also allows us and ARM to tape out reference chips with each other’s IP in it. Q: What can you do now—going forward—that you couldn’t before the agreement was struck? Lund: Well, we can build a reference SoC and tape it out with an ARM core in it and we can do that much more quickly than before. We can give our IP cores to ARM so they can pre-integrate them into their reference solutions much more quickly than before. They can, in turn, distribute that to their ecosystem so their ecosystem can use this to verify software drivers and other integration aspects of this, so it’s a very significant deal and a great exposure to our IP cores. Q: And the battle to wrestle system design complexity to the ground continues. Lund: It certainly does. At the end of the day, this is about reducing complexity every day, every step of the way. We are trying to make sure that we are supporting the latest and greatest innovations that ARM has and they can take advantage of ours as well. There are new AMBA protocols coming out that have new features; there are new things in our portfolio—USB, PCI Express, and dual-mode DDR/LPDDR cores—that accelerate the performance and reduce power consumption. By ARM taking advantage of that and Cadence taking advantage of the new protocol features, a joint solution can be even more competitive. Q: And this is a significant advantage, yes? Lund: It brings significant advantages to our customers. It gives a lot of peace of mind in risk mitigation and effort mitigation and also in terms of being able to develop software stacks and so forth before you have your own chips in house. That, in turn, frees up resources so people can go innovate even more and focus on aspects of their designs that matter, versus spending all their time on integration. Brian Fuller Related stories : — Cadence at CES 2015: The IP Story — Q&A: Martin Lund Updates Cadence IP Progress, and Introduces New Website![]()
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