Link training is the first stepping stone to enabling the communication channel between source and sink devices. This is where the electrical characteristics of the link along with the bitrate are fixed, and are subsequently used for the data transfers. Here the challenge for the verification engineers lies in verifying the designs for numerous combinations that are possible in the link training process. Link training between DisplayPort source and sink devices consists of two distinct tasks that must be completed successfully and in sequence, to establish the link before frame transfers can be initiated by the source. These tasks are clock recovery and channel equalization/symbol-lock/inter-lane alignment: Clock recovery phase Clock recovery is the operation of recovering the link clock from the link data stream being sent by the source. This circumvents the need of any external clock for the sink to recover the data being sent bysSource. In this stage, the sink receiver locks the clock recovery PLL to the repetition of D10.2 data symbols which are sent by the source. The repetition of D10.2 symbols is called TPS1 pattern. D10.2 symbols carry the bit transitions (from 0 to 1, and vice-versa) every bit interval, which make them most suitable for clock recovery at the receiver end. Channel equalization/symbol-lock/inter-lane alignment phase Equalization is needed to recover the symbols sent by the source. Symbol-lock and inter-lane alignment must be achieved by the end of this phase. Source sends series of data and control symbols to the sink, for the sink to lock to the symbols and do inter-lane alignment. These series are either TPS2 (comprised of K28.5, D11.6 and D10.2) or TPS3 (comprised of K28.5, D10.2 and D30.3) pattern. During these two processes, the source device gets information about status of clock recovery and equalization from the sink device’s DisplayPort configuration data (DPCD), and determines the appropriate level of voltage-swing and pre-emphasis levels, and link bitrate, that should be used to transfer the video data, to it. In the clock recovery process, the transmitter must start signaling at voltage swing level 0, pre-emphasis level 0, and then move on to higher levels as per the indications from the sink device. Following the clock recovery phase, the equalization phase starts with transmitter drive settings as set at the end of the clock recovery phase. In both processes, the sink device indicates higher levels of voltage-swing or pre-emphasis level through the DPCD registers. If the clock recovery or equalization does not succeed even with the maximum levels of voltage swing and pre-emphasis, the source must down-shift to a lower bitrate to re-attempt the link training at the lower bitrate. The whole process of link training gives rise to several verification scenarios and their permutation and combinations. Dimensions to take care of for these verification scenarios are number of lanes (1, 2 or 4), voltage-swing levels (0, 1, 2 and 3), pre-emphasis levels (0, 1, 2, and 3), and link rate. DisplayPort Source VIP and Sink VIP enable these verification scenarios by modeling DPCD register space, supporting various link-rates, and registers to mimic requests for different levels for voltage-swing and pre-emphasis levels. These will be discussed in an upcoming blog post. Neelabh Singh![]()
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