There are many venues throughout the year where you can learn about individual EDA tools, but very few that focus on challenges and opportunities in the overall IC and system-level design flow. There also aren’t many interactive workshops that bring together electronic design experts from industry and academia. But you’ll find such an event at the Electronic Design Process Symposium ( EDPS 2015 ), planned for April 23-24 in Monterey, California. For the second year in a row Aparna Dey (right), technical marketing director for standards at Cadence, is the EDPS general chair. The symposium “fosters the free exchange of ideas among the top thinkers, movers, and shakers who focus on how chips and systems are designed in the electronics industry,” she said. “It provides a forum for this cross-section of the design community to discuss state-of-the art improvements to electronic design processes and CAD methodologies.” Now in its 22 nd year, the symposium is sponsored by the IEEE Computer Society of Silicon Valley (CS-SCV), Design Automation Technical Committee (DATC), and Council on Electronic Design Automation (CEDA). The symposium is held at the Monterey Beach Resort , where the sound of crashing surf is always in the background. But the presentations will hold your interest, and the workshop is small and informal enough (typically around 50 participants) to allow a lot of interaction. Topics for the first day, Thursday April 23, include FinFET versus FDSOI (fully depleted silicon on insulator), multi-die design, and hybrid virtual platforms. The second day, Friday April 24, is completely devoted to low-power design and includes two keynotes, a technical session, and a panel discussion. “If you need to know where the industry is and where it’s going with respect to design and development, you should consider attending this year,” Dey said. EDPS 2014 session at the Monterey Beach Hotel EDPS 2015 Program Summary Thursday, April 23 Session 1: FinFET vs. FDSOI – Which is the Right One for Your Design? Tom Dillinger, CAD Technology Manager at Oracle, is the keynote speaker and panel moderator. Blogger and consultant Daniel Nenni is session chair. Speakers from Samsung, STMicroelectronics, Synapse Design, and GLOBALFOUNDRIES. Session 2: Multi-Die Design Challenges and Applications. Consultant Herb Reiter is session chair. Speakers from Cadence, Mentor, ASE. Session 3: Hybrid Virtual Platforms . Analyst Gary Smith is session chair. Speakers from Intel, NVidia, Cadence, Mentor. Dinner Speaker: Dileep Bhandarkar, vice president of technology at Qualcomm, “The Yellow Brick Road of Semiconductor Technology.” Friday, April 24 Low-Power Design Keynote : Jim Kardach, director of integrated products at FinSix, “Low-Power Design, Standards and Evolution.” Session 4: Low-Power Technologies and Ecosystems . Naresh Sehgal, Intel, is session chair. Speakers from Cadence, Synopsys, Atrenta, and eSilicon. Session 5: Keynote . Andrew Kahng, U. of California at San Diego, “EDA/ESL Low-Power Design Trends, ITRS/CAD and Tools.” Session 6: Low-Power Panel: Low-Power Tools, Techniques, and Verification . Naresh Sehgal is session chair. Brian Fuller, editor-in-chief at Cadence, is panel moderator. Panelists from Cadence, Atrenta, FinSix, eSilicon, and Synopsys. Registration includes breakfasts, lunches, and a banquet dinner. “Early bird” rates are available until March 31. For further information and registration, see the EDPS 2015 web site . Richard Goering Cadence blog coverage of EDPS 2014 EDPS 2014: Rethinking the Electronic System Level Design Flow EDPS 2014: Creative Ways to Use Pre-Silicon Prototyping Platforms EDPS 2014 Keynote: What Intel Needs from Pre-Silicon Prototyping The Road to 1 Million Tapeouts![]()
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