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Computational Origami
At the recent Decoding Formal Club meeting, organized by Oski and sponsored by Cadence, there was a presentation on computational origami. That sounds like a great marketing name for formal...
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Logical Equivalence Checking to Get Smart
In the late 1960s and early 1970s, there was a TV show called "Get Smart." It was a sort of cross between a James Bond movie, and a Mel Brooks movie, not least because it was created by Mel Brooks....
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Shorten Your Time to Market! Get Started with Training Bytes
How can you become an expert in your field? Access our short self-help videos called Training Bytes. It’s as easy as 1, 2, 3... We know time to market is crucial. Our training team is working around...
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Disruption and Opportunity: CDNLive Korea, 2017
On September 17th, 2017, Ian Dennison (Sr Group Director R&D, CAS Product Marketing, Cadence) presented a fascinating keynote on industry trends, challenges, and opportunities in electronic design....
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Grace Hopper Celebration of Women in Computing
Last week was the Grace Hopper Celebration of Women in Computing (GHC), held in Orlando Florida (it moves around each year). It was created by Telle Whitney and Anita Borg back in 1994. Anita died in...
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Whiteboard Wednesdays - Automotive Memory Trends and Technologies
In this week's Whiteboard Wednesdays, the first in a three-part series, Scott Jacobson takes a closer look and the market size of the automotive electronics industry and how this industry segment...
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The Rise of the China IC Industry
At the SEMI Strategic Materials Conference, SMC, Lung Chu, who heads up SEMI China (and worked at Cadence at one point in his career) talked about The Rise of China IC Industry: Challenges and...
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What's For Breakfast? Video Preview October 16th to 20th 2017
(Please visit the site to view this video) Coming from a cartoon world (camera Sean) Monday: Are We There Yet? Metric Driven Signoff Tuesday: The Empire Long Divided Must Unite Wednesday: Mark...
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Linley Gwennap on the Microprocessor Market
Linley Gewennap always gives the opening keynote for the Linley Microprocessor Conference. This year, he titled it Processor Innovation Supersedes Moore's Law . The basic theme was something that I've...
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Celebrating Five Years of Performance-Optimized Arm-Based SoCs
Now including AMBA5! It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest...
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Signal Integrity Methodology for Multi-Gigabit Serial Link Interfaces
As data rates for serial link interfaces such as PCI Express ® (PCIe ® ) Gen 4 move into the double-digit gigabit transfer rates, device modeling, interconnect modeling, and analysis methodologies must...
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Rowen on Vision, Innovation, and the Deep Learning Explosion
The keynote for the second day of the Linley Processor Conference was by Chris Rowen. Chris was the founder of Tensilica, and became the CTO of the IP group when Cadence acquired them. A year or so...
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Virtuosity: Can I Speed up My Plots?
If your Virtuoso ® ADE Assembler, Virtuoso ® ADE Explorer or Virtuoso ® Analog Design Environment XL setup contains multiple sweeps or corner points, or maybe the transient simulations are time...
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Safe as Houses: Voltus and Your Aggressive Neighbor
“A good neighbor increases the value of your property.” —Czech proverb Have you ever thought about the phrase, “safe as houses”? What could be safer than being curled up in your toasty warm house,...
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Teradyne "Formally" Adopts JasperGold FPV
CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation, Success using Formal Verification --and now they join the ever-growing fold of JasperGold FPV (Formal Property...
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Teradyne Standardizes on Xcelium Simulator
Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator for use in ASIC development. They’ve reached a 2x speedup with Xcelium when compared to their old simulation solution....
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The Art of Analog Design Part 5: Mismatch Analysis II
In Part 4 of the series, we looked at applying mismatch analysis as a design tool. In Part 5, we will continue to look at mismatch analysis by applying the technology to other types of designs.. The...
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The Art of Analog Design Part 4: Mismatch Analysis
In Part 3 , we started to explore how to analyze the results of Monte Carlo analysis. In Part 4, we will consider the question, what is the relationship between process variation and the circuit’s...
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Are We There Yet? Metric-Driven Signoff
Are we there yet? All verification suffers from the problem of trying to decide when enough verification has been done. It is not possible to exhaustively simulate everything on a chip and so...
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Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 3...
Here we conclude the blog series and highlight the results of Mediatek 's use of Cadence Perspec™ System Verifier for their SoC level verification. In case you missed it, Part 1 of the blog is here ,...
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