The 2019 Jasper User Group
Last week was the Jasper User Group meeting, the biggest annual gathering of formal verification engineers. This is the 13th meeting. Ziyad recalled the first, held at the TechMart, to which about...
View ArticleVirtuoso Meets Maxwell: Help With Electromagnetic Analysis - Part III
'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® RF and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now, Virtuoso... [[ Click on the...
View ArticleAsking Our Employees: What Makes Us Great in Europe?
As the project manager of our global Great Place to Work programs, I’ve had the opportunity to attend the annual Great Place to Work Conference in Greece and Sweden where they’ve announced their top......
View ArticleIC Packagers: Plan Your Escape with Modernized Structures
Many of you, our regular readers, are familiar with via structures. These reusable patterns of vias, clines, shape, and keep-out shapes, and return path elements allow you to escape a single pin...
View ArticleDie-to-Die Interconnect: The UltraLink D2D PHY IP
One of the big trends that has been happening somewhat below the radar is the growth of various forms of 3D packaging. I noted this at HOT CHIPS in summer, when a big percentage of the designs were......
View ArticleVirtuosity: Usability Enhancements in the Property Editor
We live in a world where the idea of usability is to make products easy to use, make things easily accessible, and visually appealing. In our constant endeavor to improve the usability of our... [[...
View ArticleWhat Does P≠NP Mean?
Recently I wrote about computational software and said that EDA algorithms are all "intractable". That was in the post Computational Software. What does intractable mean? If you know... [[ Click on the...
View ArticleSuccessful Speaker Event—Engaging with Professor in Shanghai
The Cadence Academic Network hosted an Academic Speaker Series event, in collaboration with the Shanghai Site Technical Talk series, in Cadence Shanghai Office. The talk attracted more than 150... [[...
View ArticleOpenROAD: Open-Source EDA from RTL to GDSII
OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow, using only open-source software. The goal is to go from RTL to GDSII fully automatically. In a leading-edge process......
View ArticleBoardSurfers: What's Happening Around 17.4-2019?
Allegro® and OrCAD® 17.4-2019 was released on October 18 and we have since then been getting a lot of queries about a lot of things. How do I install the products? What are the system... [[ Click on...
View ArticleCADathlon at ICCAD 2019
Last week , I visited the Cadathlon@ICCAD event at the 2019 International Conference on Computer Aided Design . It was my first CADathlon and I was quite intrigued , since the organizers webpage... [[...
View ArticleFormally Verifying Processor Security
Intel has had a couple of major events that totally changed their attitude to verification. The first was in 1994 when they had the Pentium floating-point divide bug. This caused Intel to take a... [[...
View ArticleVirtuoso Meets Maxwell: Package PDK in Virtuoso! How Is It Even Possible?...
'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® RF Solution and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now,... [[ Click on the...
View ArticleVerifying Processor Security, Part 2
This is the second post about Eli Singerman's keynote at the recent Jasper User Group. The first was Formally Verifying Processor Security. In the last couple of years, high-performance... [[ Click on...
View ArticleBoardSurfers: Power of Information – Quickly Getting Started with Allegro and...
The Allegro® and OrCAD® 17.4 release is now available for download and installation. Many of you must have already started using it and many more of you must be planning to install it in... [[ Click on...
View ArticleIC Packagers: A Cross-Section of Changes
While 17.4 has only been amongst you for a month, now, I’ve had a few questions regarding manipulating your layer stack-up in the new release. We covered scripting changes previously, but a quick... [[...
View Article2nd WOSET Workshop on Open-Source EDA
During ICCAD earlier in the month, there was the 2nd WOSET, which stands for Workshop on Open-Source EDA Technology. I wasn't there but Anton Klotz, who runs the Cadence Academic Network in... [[ Click...
View ArticleLibrary Characterization Tidbits: Basics of Standard Cell Characterization...
Hey, it’s Thursday! Time to keep the promise of bringing to your Inbox some quick bit about an existing or newly introduced library characterization feature, news, or related update through this... [[...
View ArticleImplementing Arm Hercules with Digital Full Flow
At Arm TechCon there was a joint presentation by Arm, Cadence, and Samsung Foundry about implementing Arm's next-generation high-performance CPU in Samsung's 5nm process. The diagram below,... [[ Click...
View ArticleVirtuosity: Sharing Expressions between Pre- and Post-Layout Simulations
This has been an age old problem, you extract your design and get a DSPF file, then you want to run simulation in Virtuoso® ADE Assembler , or Virtuoso® ADE Explorer , using that DSPF file,... [[ Click...
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