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Don’t Miss Embedded Vision Summit on May 12
One of the best, most insightful (no pun intended) conferences each year is the Embedded Vision Summit , May 12, 2015, at the Santa Clara Convention Center, not far from Cadence’s HQ offices. If you...
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Whiteboard Wednesdays—DDR Subsystems and Latency
In this week's Whiteboard Wednesdays video, Lou Ternullo discusses DDR subsystems and their effect on latency. (Please visit the site to view this video)
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Expert Series: A New Way to Get Smart on Electronics Design Technologies
True or false: The most important thing to control in serial ink routing is the impedance tolerance of the traces. Will tighter impedance control of traces typically be achieved on external or internet...
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Moore’s Law 2.0–How Small It Is To Be A 14nm FinFET
As I mentioned in my Blog on April 7, Moore’s law will turn 50 on April 19 . What I did not emphasize enough in my discussion on silicon process evolution is size , or more accurately tininess . In...
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Q&A: Breaking Through the Verification Debug Bottleneck
The EDA industry provides impressive tools for block-level verification test generation, but has so far produced limited automation for debugging. As a result, debug is becoming a major bottleneck in...
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What's Good About Allegro PCB Editor Suppression of Unassigned Indirect Vias?...
The suppression of unassigned indirect vias is now supported in Allegro PCB Editor 16.6, which assigns the property ‘EMB_INDIRECT_VIA_SUPPRESS’ to the Component Definition, Component Instance, or...
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Whiteboard Wednesdays – Why a New DSP is Needed to Support Today's Sensors
In this week’s Whiteboard Wednesdays, Chris Rowen highlights the requirements of the wide variety of sensors – environmental, motion, audio, and imaging. He'll cover data rates, sample rates, and...
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Think You're an Expert? Board-Design Tips and Tricks
In the first two episodes of our new series "So You Think You're an Expert," Cadence's Ken Willis tackled tough questions on impedance control and serial link routing. As he continues his march to...
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Five Things You Didn’t Know About High-level Synthesis
Most of you have heard about the promises of high-level synthesis (HLS). Things like improved productivity, quality of results (QoR), and verification all dominate the high-level synthesis collateral,...
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Top 10 Common Questions Regarding New Cadence Indago Debug Platform
By now, you all must have read the news that Cadence has unveiled the new Indago™ Debug Platform , which boosts debugging productivity by up to 50%. What's the secret sauce between the productivity...
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Indago Debug Platform—Automating Root Cause Analysis and Leveraging Big Data
Debugging is becoming the biggest bottleneck in the IC functional verification flow, and no wonder—many verification engineering teams are spending at least 50% of their time in debug. Cadence this...
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EDPS 2015: Why “Hybrid” Platforms are Needed for Pre-Silicon Hardware and...
In the past few years, it has become clear that no single development platform will fulfill all the needs of system-on-chip (SoC) designers and programmers who must do their work before silicon is...
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Whiteboard Wednesdays - Analog Front-End Interfaces Explained
In this week's Whiteboard Wednesdays video, Bob Salem takes a closer look at analog front-end interfaces and why they are important for the wireless communications market. (Please visit the site to...
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Think You're an Expert Series: Will We Crown a New High-Speed Design Expert?
Ken Willis, product engineering director for high-speed signal analysis products at Cadence, has sweated his way through three episodes of So You Think You’re an Expert, our new series testing domain...
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The Time is Ripe—SystemVerilog Adoption for Design Is Gaining Momentum
On March 2, 2015, I had the privilege of moderating the Accelera tutorial at DVCon San Jose , which focused on the adoption challenges and the benefits of using SystemVerilog for design (SVD). The...
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EDPS 2015: Have We Hit the Power Floor?
When it comes to pushing power as low as it can go, the answer is part technological, part cultural. That was the conclusion of a panel of experts at the annual Electronic Design Processes Symposium in...
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EDPS 2015: Choosing FinFET, FD-SOI, or Bulk Planar FETs (Part 1)
If you’re designing an IC today, you have three types of transistors to choose from – traditional bulk planar FETs (down to 20nm), FinFETs (below 20nm), and FD-SOI (fully depleted silicon-on-insulator,...
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EDPS 2015: Choosing FinFET, FD-SOI, or Bulk Planar FETs (Part 2)
Will you use FinFET or FD-SOI (fully depleted silicon-on-insulator) technology in your next IC design? At a panel discussion at the recent Electronic Design Process Symposium ( EDPS 2015 ), industry...
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Speed, Function, and Technology as Key Factors for USB Applications
USB is regarded as the world’s most popular serial interface, with over 1 billion devices shipping every year. This means there are a lot of players in the market, and many possible applications. From...
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What's Good About the Allegro Design Entry HDL Front to Back Flow Cadence...
Hear what Bruce Imai—a Cadence Educational Services course developer—Cadence Application Engineers, and customers have to say about the valuable content available in our Allegro Design Entry HDL Front...
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