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Q&A: Clearing the Obstacles to Electrical Signoff
One of Alessandra Nardi’s favorite quotes is, “You can’t direct the wind, but you can adjust the sails.” An R&D group director on Cadence’s electrical signoff team, Nardi is inspired by the...
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The Design that Made ARM
I sat down with Simon Segars, the CEO of ARM last Friday. As I said yesterday , it is ARM's 25th birthday this week, on Friday if you want the precise date. Although today, of course, we think of even...
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Cheating Tetris
Remember Tetris? We’ve all played it at some point in our lives. You know, the game with falling blocks of different sizes and shapes where you have to place the incoming blocks in an optimal way to...
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50 Gbps Ethernet is on the Way
Here is my report from the most recent IEEE 802.3 standards meeting, which was held in Dallas during the week of November 9. The big news is that work on 50G Ethernet is now about to start. The 25G...
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Voltus-Fi: Faithful Custom and Analog EMIR and Power Analysis
First things first. Voltus and Voltus-Fi are two separate products. They are both used for EMIR analysis, Voltus for digital design and Voltus-Fi for analog design (or custom transistor-level digital),...
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Can You Pass As a Brit? Just Answer 3 Simple Questions
It’s Thankgiving! Happy Thanksgiving if you are reading this on the day. Cadence is closed, of course. I’m working on blogs for next week (yeah, right). But I thought I’d put out a fun blog. This has...
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TSMC 3D. Red and Green Glasses Not Required
I have been taking a look at TSMC's 3D packaging technologies. From numerous presentations at OIP and the Technology Symposiums, I knew that they had two. CoWoS and InFO and I knew...well, that's about...
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Q&A: Love of Math Adds Up to Passion for Formal Verification
Exhaustive and comparatively efficient, formal verification is a powerful option to other verification methods because it can detect bugs much earlier in the design cycle. Anyone with a love for math,...
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Take Tighter Control Over Your Shape Degassing Patterns with Cadence 16.6...
With metal density and balancing requirements getting stricter with every year that passes, how you perforate the plane shapes of your designs needs to adapt. Whether it is a new hole shape that allows...
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Virtuoso: Advance to 10nm, If You Pass Go Collect $200
There are two major discontinuities in the last couple of process nodes—FinFETs and multiple patterning—which have changed a lot of the rules for custom design (which doesn't just mean analog, but also...
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Will USB Type-C Connector Replace the 3.5mm Audio Jack?
In the past few days, there have been many posts on the Internet around Apple planning to remove the 3.5mm audio jack support from the upcoming iPhone 7 to create the slimmest iPhone in history. Given...
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Whiteboard Wednesdays—DUT Verification with Cadence VIP
In this week's Whiteboard Wednesday's video, Arindam Guhu explains how to quickly start DUT integration with Cadence's Verification IP (VIP). (Please visit the site to view this video)
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Why Do Layout Designers Say "Stream Out"?
For the same reason we "hang up" our phones. When a layout designer saves a design, they often say "stream out" whereas in most software, such as Word or Powerpoint, this is usually simply called...
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What's Good About PCB Allegro Rules Developer and Checker? 16.6 Has It!
You can now leverage the 16.6-2015 release Allegro Rules Developer and Checker . The Allegro Rules Developer and Checker allows you to develop custom fabrication and assembly rules to extend...
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Cadence Innovus Implementation System is Available to Academia
To support academia using the latest industry-standard tools, Innovus™ Implementation System has been made available to universities. If you want to use Innovus Implementation System, please contact...
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Cadence Academic Network - The Next Generation
“University students around the world are using Cadence technology to learn and develop their talents. The future of EDA is bright… and very friendly!” – Patrick Haspel, Senior Principal Program...
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Front-end Design Summit
Wednesday was the annual Front-end Design Summit at Cadence headquarters. This focuses on the digital front-end design tools, which means synthesis, test, and power. Almost any semiconductor seminar...
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Cadence Innovus Implementation System is Available to Academia
To support academia using the latest industry-standard tools, Innovus™ Implementation System has been made available to universities. If you want to use Innovus Implementation System, please contact...
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Digital Designers Discuss Ways to Close the Power Gap for Wearable Devices
How often do you have to charge your electronic devices? What is often an annoying problem for consumers is an even more vexing challenge for the engineers who design wearable devices. A panel of...
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Xtensa Design Contest 2015 in India
The Cadence® Xtensa® Design Contest is an initiative of the Cadence India University Program and the first such initiative of this kind. In this contest, students are provided with a project problem...
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