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Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and...
Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and...
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CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and...
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given...
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Customer Support Recommended – Pin Swapping in Allegro Design Entry CIS and...
Placement and routing have always been an integral part of printed circuit board design. The productivity of the product is often (if not always) achieved best if the PCB has a proper placement of the...
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SKILL for the Skilled: Many Ways to Sum a List (Part 6)
In a previous post I presented sumlist_2b as a function that would sum lists of length 0, 1, or more. (defun sumlist_2b (numbers) (apply plus 0 0 numbers))Unfortunately sumlist_2b cannot handle...
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Library "Safe Margins" -- Are They Really Saving Your Design?
Designers need to radically re-think their strategies for timing closure to get the most out of process technologies that are becoming readily available. The additional burdens of creating electrical...
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User Video and Presentation: Mixed-Signal Design Using OpenAccess
A distinctive aspect of the Cadence Mixed-Signal Solution is the use of the OpenAccess database to integrate custom/analog (Virtuoso) with digital (Encounter Digital Implementation System) design....
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Virtuosity: 10 Things I Learned in December By Browsing Cadence Online Support
In addition to the R&D engineers who actually develop our software, the folks in many other groups here at Cadence put a lot of time and effort into creating a wide variety of documents,...
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Five-Minute Tutorial: Creating An EM Model File
One of the least-fun parts of running power and rail analysis has always been coming up with the electromigration (EM) model file. In the past, this involved cracking open the process design rule...
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Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two...
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What's Good About Viewing Constraint Differences? See for Yourself in Allegro...
Starting with the Allegro PCB Editor 16.6 release, we can compare two constraint databases and view the constraint differences. This provides an efficient opportunity for designers to determine the...
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2013 CES: Top 4 Trends Benefiting EDA
While a variety of EDA customer segments are growing, consumer electronics continues to drive the lion's share EDA of industry revenues. Hence, many events at last week's annual Consumer Electronics...
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Make Your IC Packaging Documentation Labels Smarter with 16.6 SiP and APD
Documentation is key when completing any IC package substrate design. Without it, any number of problems can arise - from incorrect bond mapping between die pads and bond fingers to die being stacked...
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BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor
A 3D multi-gate transistor called the FinFET promises tremendous power and performance advantages at 16nm and 14nm process nodes (and was adopted at 22nm by Intel) -- but nobody can use FinFETs without...
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Specman: An Assumed Generation Issue and its Real Root Cause
Random generation is always a complex task, and differences in results are usually very hard to debug. Besides, generation misbehavior always rings many bells in R&D :-)A customer reported a random...
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What's Good About DEHDL’s Interface Aware Design? The Secret's in the 16.6...
Components in a design communicate with each other based on some rules or protocols. These protocols contain a group of signals with some relationships defined between them -- for example byte lanes,...
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Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic
3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian...
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A 10-year Look-Back from 2013 – Some Technology Predictions that are Coming...
It is January 2013, the year has begun and it is time for my annual 10 year look-back to see how well technology predictions have been implemented or missed (you can find last year's look-back here )....
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DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference (DVCon 2013) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design...
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A Concrete Linux Virtual Platform Example
Virtual platforms are used to find many different types of system and software issues. Of course, platforms take some time to develop and debug (regardless of what you read in marketing brochures), but...
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Introduction to Cadence Virtuoso Advanced Node Design Environment
What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development...
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