The new release of the Virtuoso platform (*ICADVM18.1) offers groundbreaking analysis capabilities and an innovational new simulation-driven layout for more robust and efficient design implementation as well as extending our support for the most advanced process technologies. With this solution, we are able to significantly improve productivity through advanced methodologies and provide the most comprehensive set of solutions in the industry with an interoperable flow across chip, package, module and board. *This feature will also be available in IC6.1.8 for mature nodes. You spoke and we listened. You wanted a system to aid the communication between schematic and layout designers, who are often situated in different buildings, countries, or time zones. Where design goals can be defined and discussed, implementation restrictions resolved, and decisions agreed and recorded to prevent duplication of effort during design reuse. Cadence brings you… Virtuoso Design Intent, a new capability to complement the Virtuoso Schematic Editor XL and Virtuoso Layout Suite XL applications. Liberating designers Virtuoso Design Intent facilitates and captures the communication between the schematic designer specifying design goals and the layout designer implementing and achieving those goals. Schematic designers focus on capturing their design intent without having to create physical constraints on the design. This doesn’t mean farewell to Virtuoso Unified Custom Constraints; instead layout designers now have the freedom to decide how to physically implement and achieve the design intent. Read on to discover a little more about Virtuoso Design Intent and we will return to how it complements the constraints flow. The Design Intent flow The flow of Virtuoso Design Intent is contained within Schematics XL and Layout XL and requires interaction between the schematic and layout designers for a design. Schematic designer selects an object or group of objects to have a design intent added (e.g. device matching requirements, noisy/sensitive nets, high currents, voltage drops, pin information). They capture their design goals on the Create Design Intent form using a combination of text notes and predefined property profiles, which contain frequently used design intent specific properties that formalize their design goals e.g. add shield, add guard ring, and so on. Each design intent is stored in the schematic and is displayed as an easily identifiable, colored annotation on the canvas. The created design intents are transferred (synced) to Virtuoso Layout XL and from then on design intent changes are updated on the design, visible in both Schematics XL and Layout XL. Layout designers can clearly identify the objects specified with design intents and begin implementing each intent. Using the Edit Design Intent form, they can update the current implementation stage and add implementation notes or queries to communicate back to the schematic designer. By regularly syncing, the schematic designer is updated on the implementation progress of each design intent in the design. Via the Edit Design Intent form, they can respond to any queries or comments recorded by the layout designer, adapting the intent if required and ultimately signing off on the implementation of their design intent. Progress of all the design intent implementation on a design can be checked at any point using a high-level summary report generated from either Schematics XL or Layout XL. What about the existing Virtuoso Unified Custom Constraints flow? If you are familiar with Virtuoso Unified Custom Constraints, our interactive and automated constraint-driven tool, you’ll be aware that it assists you in creating error free designs across the Schematics XL and Layout XL applications. Each constraint on a design is a physical or electrical rule defined by you to help you achieve your design goals. Virtuoso Design Intent complements the existing Constraints flows by capturing the schematic designer’s requirements at a higher level, enabling them to communicate their requirements to layout engineers without overlapping their roles. By using Virtuoso Design Intent to capture design goals, Constraints can be used to focus purely on defining the specific rules that are required to satisfy and implement the designer’s original intent. Sound good? It looks even better… Watch out for our upcoming Virtuoso platform ICADVM18.1 and IC6.1.8 releases. Contact Us For more information on What’s New in Virtuoso ICADVM18.1 and IC6.1.8 releases, see What's New in Virtuoso . For more information on Cadence Custom IC/Analog/RF Design products and solutions, visit www.cadence.com . For more information on the New Virtuoso Design Platform, or if you have any questions or feedback on the features covered in this blog, please contact team_virtuoso@cadence.com . If you would like to receive similar updates about what new and exciting features are being built into Virtuoso for our upcoming Advanced Nodes and Advanced Methodologies releases, enter your email ID in the Subscriptions field at the top of the page and click SUBSCRIBE NOW. Sarah Finlayson, Gautam Kumar and Mark Baker![]()
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Virtuoso: The Next Overture – Introducing Design Intent
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6 Reasons To Register for CDNLive India Today!
CDNLive India 2018 is just around the corner! In a few weeks’ time, on the 6th and 7th of September, CDNLive India will host Cadence technology users, developers, and industry experts for two days of learning, networking and fun! If that’s not exciting enough, here are six more reasons as to why you should clear your schedules and make your way to the most happening event covering advanced silicon, SoCs, and systems. 1. World-class keynotes, including by Cadence CEO Lip-Bu Tan and Sr VP Babu Mandava CDNLive 2018 feature keynote speeches by senior Cadence executives as well as industry leaders - Subhash Chandar G from TI on Sep 6 and Govind Malalur from Broadcom on Sep 7. Be sure you are there for the keynote speeches which are scheduled to start at 9.25 AM on both days, following the welcome address by Jaswinder Ahuja, Corporate Vice President and India Managing Director, Cadence Design Systems. 2. 90+ technical user presentations Here’s your chance to discover how other users like yourself are using Cadence technologies and techniques. Learn to solve design challenges and speed up processes across all aspects of design and IP creation, integration, and verification. Analog Devices, Arm, Broadcom, Invecas, MediaTek, NXP, Qualcomm, STMicro, Texas Instruments are just some of the companies that will be presenting. 3. Real-time information at your fingertips If you have not yet downloaded the CDNLive app, do it now, because it’s got the complete agenda to help you make the most of the two days at CDNLive. Use the app to like events, post pictures and comment on activities. Plus, there is a cool Cadence cap waiting for everyone who downloads the app. 4. A view of the latest technologies at the Designer Expo The Designer Expo exhibition not only showcases the latest in Cadence technologies, but also the latest offerings from our exhibitors and sponsors. The Designer Expo is open from 12noon to 5PM on both days. 5. A Google Home Mini and Amazon Echo and many other goodies to be won! Some amount of work and a little bit of luck—that’s all you need to win a Google Home Mini and Amazon Echo. Keep posting your pictures and comments, as the top 20 on the Leaderboard each day will be entered into a lucky draw for a Google Home Mini. And don’t forget to get your Designer Expo passport game card stamped when you make your rounds to visit booths at the Designer Expo. Get 10 stamps on your passport game card and you can enter into a lucky draw to win an Amazon Echo. 6. A chance to network, network, network! Your chance to meet, greet and establish vital business connections has just gone up a notch! Use your tea and lunch breaks to reach out to speakers, exhibitors and fellow attendees whose common point of focus is advanced silicon, SoCs, and systems. V Visit the CDNLive India page to register. Looking forward to seeing you there!![]()
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Chaos, Fractals, and The Theory of Unintended Consequences
“Prediction is difficult, especially the future.” — Niels Bohr Okay, in my post last week , I revealed that I was a deterministic Newtonian, and my reasoning was about two hundred years old. I posited, “If I could identify all the forces and weights and measures of a leaf blowing in the wind, what’s to prevent me from hooking into the local quantum computer to predict exactly how that leaf will behave as it is falling to the ground?” It seemed to me—and to Sir Isaac Newton— that this should be possible. Newton believed that every interaction of bodies and force should be able to be predicted and determined using mathematics. Newton’s Cradle: We all know what happens next This is what calculus is all about, right? I thought that made intuitive sense. Scientists and mathematicians agreed with me—up until the end of the 1800s when they uncovered some difficult equations non-linear differential equations to solve; in particular, the horribly difficult and outstanding problem of predicting the behavior of three mutually gravitationally attracted bodies—the so-called “three-body problem”. Turns out, this can’t be solved (or, at least, not yet). The Three-Body Problem: We can’t predict with 100% accuracy what will happen next A Quantum World And here’s the rub: we don’t live in a Newtonian world. We live in a quantum one. You simply can’t model how any leaf behaves in the wind because they are made up of molecules, and you can’t model every molecule accurately because you don’t know the position and velocity of every particle because of …irony, irony, (because I was talking about the power of quantum computing)… quantum mechanics. It is fundamentally not possible to model the world to arbitrary accuracy. And that makes intuitive sense, too. Of course it’s true (and thank you, Paul , for first pointing this out to me in a way that I could understand). No matter how much quantum computing power we have access to, quantum physics itself prevents us from making mathematical models to predict anything with 100% accuracy. We can make models that approximate the behavior of complex systems, but before too much time passes after we begin the model, the accuracy of that model will degrade. This is chaos theory—the theory that within the apparent randomness of chaotic complex systems, there are underlying patterns, constant feedback loops, repetition, self-similarity, fractals, self-organization, and reliance on programming at the initial point known as sensitive dependence on initial conditions (thank you, Wikipedia ). This is why weather models’ predictions degrade after a few days; the tiniest variable (such as the flap of a butterfly wing in China) at the beginning of the model may affect the grandest of systems (say, a hurricane in Texas), to the point that the model becomes useless. Chaos is indeterminism at its core, embodying three important principles: Extreme sensitivity to initial conditions Cause and effect are not proportional (take that , Newton) Nonlinearity This indeterminism forms the basis of the fact that there will never be any universal equation, and we will never be able to predict the future with any kind of real accuracy. Fractals You know what a fractal is—a fractal is a geometric object that is like itself on all scales. If you zoom in on a fractal object it will look exactly like the original shape. This property is called self-similarity. Examples of Fractals. Left: Constructing a Sierpinski triangle ; Center, a Koch Snowflake; Right, a Barnsley Fern (A neat thing about a Koch Snowflake and a Barnsley Fern is that they enclose a finite area with an infinite perimeter! Now you know the answer when the question comes up on your next trivia night.) You see examples of fractals all over the place, from the growth of a tree to the way a river behaves to swirls in a seashell to how a mountain forms. Fractals are infinitely complex patterns that are self-similar across different scales. They are created by repeating a simple process over and over in an ongoing feedback loop. Driven by recursion, fractals are images of dynamic systems—the pictures of chaos. Back to the Future, and Another Kind of Butterfly Effect I love time travel stories, although chaos theory would never permit it. (Suspension of disbelief is a powerful force.) In Back to the Future , can you imagine the fallout of the smallest event of Marty McFly going back to 1955? Think of the very first thing that happened when he went back in time: www.youtube.com/watch He hits a scarecrow and then crashes in the barn of a local farmer. But think of the birds that wouldn’t have been scared off by the scarecrow the following day, which led the birds to eat grain in another field, which led to a lower grain yield of the other field, which led to something else… Or imagine the time that the farmer had to spend cleaning up the barn was time spent that he didn’t spend doing something else that didn’t get done, which led to some other kind of consequences… Or think about the effects of the disturbed sleep of the family, which could have resulted in lower test scores of the kids the next day, which led to lower grades, which led to goodness knows what… And don’t even get me started about thinking of the effects of the family seeing what they interpret to be a space alien. These micro-events were just thrown away in the movie. (But how could they be treated with any seriousness? It was a comedy, after all.) The best treatment of time travel I have read illustrates another kind of butterfly effect: Ray Bradbury’s A Sound of Thunder , a science fiction short story first published in 1952. Long story (well, short story) shorter, the main character travels back in time to the Late Cretaceous period, and accidentally steps on a butterfly. When he returns to the present, words are spelled and spoken strangely, and a local election went a different way than before he left. The death of the butterfly had apparently set a vast series of subtle changes that affected the nature of the present. See? Chaos theory in practice. The Butterfly Effect You see it everywhere. Have you ever been stuck in traffic without any discernable cause? That’s chaos theory. About a month ago I got a flat tire in a very inconvenient and dangerous place on the highway, and police officers closed off traffic behind me, so I could limp to a safe place to put on my spare. My flat tire caused the traffic to back up, which likely caused someone to be late to a meeting, which then caused goodness-knows-what. I feel guilty about causing that traffic tie-up, but should I? It wasn’t my fault, it was the fault of whoever lost that nail that embedded itself into my tire. Fault is a ridiculous concept when you’re thinking about chaos theory. A famous proverb To Sum It Up In the last three weeks, I have been written about what quantum computing is, some possible effects of quantum computing on our world, and the limitations of unlimited computing power due to the certainty of uncertainty. I think that it’s safe to say that considering the remarkable variables that are in play in this complicated world, there will always be unintended consequences in whatever we do, whether we’re simulating an IC design or driving to work one morning. The best we can do is roll with whatever is thrown in our direction, and be aware that for every action, there is an equal and opposite reaction. Or not. Your actions can snowball. You can count on it. —Meera References Some websites that helped me to write about this stuff: http://www.abarim-publications.com/ChaosTheoryIntroduction.html#.W3IASOhKhaQ https://fractalfoundation.org/resources/what-are-fractals/ http://www.stsci.edu/~lbradley/seminar/index.html <-- this was my favorite source; chaos theory and fractals in a comprehensive, readable format https://en.wikipedia.org/wiki/A_Sound_of_Thunder https://en.wikipedia.org/wiki/Chaos_theory![]()
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CDNDrive Automotive Solutions: the Rear Wheels
Yesterday was the first of two posts about Cadence Automotive Solutions. Today we go down into the details a bit more. However, there are so many details that this will be more of a map of the landscape so you get an idea of the breadth of our technology. Each item could have a blog post all of its own, and in many cases I have already covered the topic in detail. Silicon IP Cadence has a broad IP portfolio, some of which is applicable to automotive as well as other markets, although it needs extended characterization for automotive temperature ranges and, perhaps, lifetimes. See my post Cadence Automotive IP Solutions . One key piece of IP is automotive ethernet. See my post Ethernet: Coming Soon to a Car Near You . Here I will focus on the Tensilica processor IP. General purpose microprocessors are far too slow and power hungry to handle all the processing coming from perhaps a dozen or more sensors (camera, radar, lidar, ultrasonic). The only possible approaches are to build completely hand-crafted logic, or use a specialized processor that is optimized for the particular function. There are a range of processors, some great for audio but with nowhere near enough power for video, for example. I'll just summarize the Vision C5 DSP which is a dedicated neural network processor, which can also be clustered into multiprocessor systems. It achieves 1 TMAC/s in 16nm in less than 1mm2. It can run all neural network layers, convolutional and later. For high performance, it has a 1024-bit wide memory interface. For full details see my post Vision C5 Dedicated Neural Network Processor . There is a tool flow that compiles neural networks from all the popular environments such as TensorFlow or Caffe. The lower powered Tensilica processors also have their niches, for vision or audio processing. High performance when you need it, even lower power when you don't. Functional Safety Functional safety is something that could fill dozens of blog posts. Just in case you don't know, a FIT is a failure-in-time, 1 FIT is one failure per billion hour of operation. A car should have <10 FITS. However, a silicon process has more like 500 FITS. So you immediately see the problem: how do you make a reliable car out of unreliable components. It is a similar problem to the one cloud datacenters have, where servers and storage drives fail all the time, the overall datacenter must be rock-solid. A good summary of the main functional safety process is in my post Make Sure Your Car Doesn't Break Too Often...When It Does, Make Sure You Catch It . If you have been in IC design for decades, back in the days of gate-level simulation, you may remember fault simulation from the days before scan-test and built-in-self-test (BIST). We used functional vectors to create the manufacturing test, but we still needed to make sure it was good enough. For this we used fault-simulation, which (oversimplifying) made sure that any faulty gate would be detected during manufacturing. The same basic approach, but taken to a new level, is used for automotive: make a list of all the things that might go wrong, and then make sure not that it would be detected, but that it would be handled appropriately (maybe correcting it in the case of a memory read, turning on a warning light for something not too serious, or dropping an autonomous car back into an emergency safe mode). It is easy to get a little confused in this area, since "normal operation" includes things like crashing and making sure the airbags deploy, even though most of us hope never to operate our cars that way. The acronym in this space is FMEDA, which stands for Failure Modes, Effects, and Diagnostic Analysis. This requires a whole process starting from safety requirements and FIT rates, all the way down to things like options in Innovus physical design to create safety islands, and add redundant vias. That's quite a range of areas of concern. Reliability Reliability in semiconductor has a special meaning, and doesn't mean the same as safety. It is concerned with aging of integrated circuits. This is especially acute with automotive since aging is made worse at higher temperatures, and those transistors have to last for a long time, 15-20 years. The target defect rate is very high, 0ppm. It turns out that up to 95% of all field failures are due to the analog or mixed-signal portion of products. This post is long enough already, but like on those cooking shows, I have one I made earlier. Look at Legato: Smooth Reliability for Automobiles . Find out what a bathtub curve is, if you don't already know. Summary It goes without saying, that this somewhat random seeming laundry list is in additional to the complete Cadence tool flow, these are the things that are added to a normal tool flow to make it ready to drive off the lot and start an automotive SoC design. It is by no means a complete list. Broad-based partner for automotive system design enablement Strong ADAS offering for high-performance, low-power SoCs Tensilica – the common acceleration platform for ADAS Dedicated neural network processor core incl. NN compiler ADAS Rapid Prototyping system incl. quad-core Tensilica Vision P6 Scalable Infotainment solution based on Tensilica HiFi Tensilica Processor ISO 26262 Compliance Certified ASIL B(D) Ready as SEooC ISO 26262 Processor Safety Kit Validated design flows, tools and IP for ISO 26262 compliant product design and certification Legato: Design-for-Reliability solution Sign up for Sunday Brunch, the weekly Breakfast Bytes email![]()
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What's For Breakfast? Video Preview August 20th to 24th 2018
https://youtu.be/6a0znbVfFJk \ Coming from the Cadence parking lot (camera Sean) Monday: Jobs: Farmer, Baker Tuesday: Jobs: Printer, Chocolate Maker Wednesday: Jobs: Programmer, Caver Thursday: Jobs: Some Lessons Learned Friday: Jobs: Five Lessons www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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SEMICON 5nm: 7nm Is Just a Dress-Rehearsal
Usually I don't go to the last day of SEMICON West since not much happens that day. But they have got smart, and two of the most interesting sessions took place in TechXPOT (I think you pronounce that Techspot) on Thursday. In the afternoon was Scaling Every Which Way about, basically, technologies beyond 5nm. I will cover that at a later date. In the morning, it was Lithography at 5nm and Below . This session featured: Eric Hoster of GlobalFoundries on EUV Lithography: The Next Generation Michael Lancel of ASML on Lithography for the 5nm Node and Beyond Stephen Renwick of Nikon on Advanced Nodes with 193i Lithography Christopher Progler of Photonics on EUV Mask Insertion: Confident or Compromise? Mary Ann Hockey of Brewer Science on What is Really Happening with DSA? [directed self-assembly] Neeraj Khanna of KLA Tencor on Addressing Process Control Challenges for the 5nm Node and Beyond Angelique Riley of TEL on Novel Patterning Schemes and Technologies for the Sub-5nm Era with a Focus on EUV There was obviously more material from that array of experts than I can possibly cover in a single blog post (or even several). Also, some of the presenters self-disqualified by not providing their presentations on the SEMICON website afterward. Photos of the monitors are never great at the best of times, but I was sitting off to one side so they were even more awful than normal. The first presentation, by Eric Hoster, who is GF's EUV Lead Technologist, is where I'm going to focus. He works for a foundry so is a comparatively independent observer. The next two presentations, by ASML and Nikon could be summarized as "everything is going to be okay", and "we've got your back if they're not." I'll drop in appropriate statements from other speakers, but Eric's sober assessment of how much further we need to go to make EUV work for 5nm, even given that it's working(ish) at 7nm was fascinating. Eric Hoster Eric opened with a great quote: We stand on the precipice of EUV insertion at 7nm. But 7nm is just the dress rehearsal for the next generation, which will be incredibly complex. He recalled the i-line to KrF transition, which involved the introduction of chemically amplified resists (CAR), arc lamps changed to excimer laser, and new pellicle materials. It was disruptive. The transition to the second generation of KrF lithography was much more evolutionary. But he warned that the transition to the second generation of EUV will not be like that. As he carried on to say: We've solved a lot of challenges over the last 30 years to get to this point. Now we need to look at what we need in the future. The grid on the left shows the ranking of the issues over the years for the introduction of the first generation of EUV (which is turning out to be 7nm, although everyone assumed it would be much earlier). The top worry was getting a reliable source, which seems to be on-track. But the chart on the right shows the ranking of the issues for the next generation EUV for 5nm, where the big challenge is to meet sensitivity, stochastics, and resolution simultaneously. Stochastics are pretty much the new name for line-edge-roughness (LER) since there are other things involved now. But the main tradeoff remains the same: sensitive resists, and high doses, cause big sochastic problems. Low doses, or low sensitivity get lower stochastics, but the throughput is uneconomical. If you want to go fast, you are going to have a stochastic problem. The problem for 5nm and beyond is that as you increase the resist dose, you drive down the defect density. But as you go to smaller resolution, the same number of photons are in smaller area so we need to double the sensitivity of the photoresist. If we can't do that, and we probably can't do it enough, then, "we're gonna need more photons". The effective dose has to increase a lot at every node: 40 mJ/cm 2 at 7nm, 60 mJ /cm 2 at 5nm, and 120 mJ/cm 2 at 3nm. As Eric pointed out, "we are victims of our own success since the molecular nature of matter is now relevant". For example, the photoacid generator (PAG) molecules in CAR have a spacing of 1.7nm in a high PAG-loaded resist. The variability can lead to notching and scumming (as in the picture I used at the start of this post). The adamantane molecules in the resist are 0.5nm cubes, in a process where the overlay budget (alignment error between different masks) is just 2.5nm. There are some hopes for the future, such as metal oxide resists and silsesquioxanes, which are very regular. Another resolution issue is known as scanner fleet variation: at these resolutions, every EUV scanner is a little different due to aberrations. For example, the overlay between one layer and the next is typically much better if both layers are exposed on the same machine than on two different ones, but in practice in HVM you don't have that luxury. Next Eric moved on ot look at productivity and cost of EUV. EUV is more cost-effective than optical triple-patterning for now. The next generation high-NA EUV machines will have very high cost-of-ownership (and they are two stories tall, so also impose costs on the fab construction). The tradeoff is between EUV LELE (litho-etch-litho-etch, ie double patterned EUV) versus high-NA next generation EUV, which might survive with single patterning for another node. He had a lot of detailed tables that I'm not going to reproduce here, but his conclusions were: 350W source power is needed lithography performance will remain of paramount importance Finally, he moved onto OPC/RET (optical proximity correction, resolution enhancement technology, basically working out how to put different patterns on the mask so that it prints better). This is going to get lot more complex. RET has actually got a lot simpler, first with double patterned 193i which required less than the last generation of single patterned, and EUV required even less. But we can't get to 5nm and beyond without SRAFs, sub-resolution assist features. It will requires "OPC on steroids." However, model-based implementation of SRAFs has proven difficult even in optical lithography due to computational cost, shape complexity, and output file size. EUV further adds complications of minimizing pattern displacement error and best focus shifts. Eric's finally summary slide. Just like the three most important things in real estate are location, location, location, so the three most important things in next-generation EUV are stochastics, stochastics, stochastics. Michael Lercal I won't cover all of Michael Lercal's presentation. But he works for ASML, the only company to manufacture EUV products. So their future roadmap is very important. Here is the one timeline summary: And his picture of the high-NA system architecture. Note the person on the left for scale. These things are huge. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding integration and verification time. Click to watch here .![]()
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The Brief but Spectacular History of Shockley Labs
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the companies, that created the companies that we see today. I also wrote earlier this week on The Birthplace of Silicon Valley: 391 South San Antonio Road . On Wednesday there was a celebration of the birth of Silicon Valley at its birthplace, 391 San Antonio Road in Mountain View. This is where Shockley's lab was. The original lab was a Quonson hut but was knocked down several years ago. However, the developer of the site commissioned and installed a number of monuments and statues to recognize the importance of the location, along with a 10' long plaque showing photos and the timeline of the establishment of Shockley Labs, Fairchild, and many of the Fairchildren. The event was organized by the IEEE and the City of Mountain View. The main speaker was Professor James Gibbons, a former dean of engineering at Stanford, whose first task (in 1957) was to work with Shockley and his team to transfer their silicon fabrication knowledge to Stanford, which could in turn train future engineers for what became the industry that we know today. The Brief but Spectacular History of Shockley Semiconductor Laboratory I will abbreviate Shockley Semiconductor Laboratory to SSL. The Prequel On June 26th 1948, Bell Labs filed for a patent on the bipolar junction transistor invented by Shockley. This is not the original point contact transistor, invented by Shockley, Bratten and Bardeen. This was wonderful science but not the basis for industrial manufacture. The bipolar junction transistor was not an experimental device, it was an extraordinary piece of imagination that Shockley came up with when he was bored in a three-day meeting. Then on April 7th 1949, Gordon Teal at Bell Labs used a crystal growth technique to build the first junction transistor (using germanium, not silicon). Finally, on June 1st 1955, Shockley left Bell Labs to start a company to make silicon bipolar devices (and other semiconductor devices). SSL Episode 1: 1955-57 On September 23rd 1955, Shockley received funding for 2 years from Arnold Beckman, with the promise to collect "the most creative team in the world for developing and producing transistors". Beckman wanted to set up the company in Pasadena (southern California) but Shockley wanted to set it up in Palo Alto since his aging mother lived there (at 949 Waverley Street). He rented a Quonset hut at 391 San Antonio Road, where we all were last Wednesday. It was 2255 square feet (rent was 5.5¢ per square foot). From October to the end of 1955, Shockley made good on his promise to hire the most creative team. He would just call and say: "this is Shockley calling." Everyone knew who he was. Noyce recalls thinking "I'm talking to God." He hired Noyce, Moore, Last, Hoerni, Roberts, Kleiner, Grinich, Blank. His pitch was "we will focus first on making silicon bipolar transistors." He was apparently extremely good at judging people, but he didn't trust his own judgment and was a big believer in IQ and personality tests, and made everyone take one. Noyce and Moore were "very bright but will never make good managers"! In February Beckman and Shockley announced the company, and in April the team started work. Of course, there was no equipment manufacturing industry, so they had to build everything themselves. In the fall, the seeds of the beginning of the end were planted. Shockley switched the company's principal focus to 4-layer diodes, since through his Bell Labs connections he had heard that Western Electric (the manufacturing arm of the Bell System) were tentatively planning on using them for switching, so this had the potential to be the first big market for semiconductors. Noyce and Moore argued to do silicon bipolar transistors first, and then move on to 4-layer diodes. But Shockley's mind was made up. However, there were a lot of difficulties building them, and Shockley berated employees in open meetings (Shockley's management skills were notoriously bad). However, the silicon bipiolar team still continued to develop the basic technology. In November, Shockley won the Nobel Prize for Physics for the invention of the bipolar junction transistor, along with Bardeen and Brattain for the point-contact transistor. There was a champagne brunch with the team at Rickey's. "I've never seen Shockley so happy," Jim said. As it happened, VLSI Technology's first annual Christmas party was also held there (it no longer exists, it shut down in 2005). Just one month later, on December 8th, the senior team wrote to Beckman describing the intolerable working conditions: "Please help us immediately." It was signed by the senior members of the technical staff. Beckman met with the team two days later. The team's proposal was: focus the company on silicon bipolar only appoint a new manager Shockley should take a position at Stanford and serve as technical advisor to the company, but no longer manage it Beckman appeared to agree, but then after discussion with Shockley decided to make no change. Jim thinks that the prestige of having a Nobel prize winner running the company was just too significant for Beckman to ignore. In March 1957 Moore created a repeatable process for fabricating high-quality silicon diodes, and believes that the lab is within months of having a bipolar transistor. Shockley, now 3/4 of the way through his funding, moved Last, Hoerni, and Robert to the 4-layer diode team and puts extreme pressure on everyone to succeed. Mid-May 1957, Beckman Instruments' finances are deteriorating, so he visits SSL and asks Shockley to "keep expenses down." Shockley says that he will "find new funding and take his team somewhere else." But, in what will turn out to be the beginning of the end, Gordon Moore calls Beckman, with everyone else hanging around the phone, and tells him that the transistor team will not follow Shockley anywhere. On June 1st, Beckman tells Shockley that the team will not follow him anyway, but will stay at SSL if Shockley himself goes. But once again Beckman chooses Shockley over the team. But Moore and the team realize that they have burned their bridges and prepare to resign individually and look for new employment. Sometime in July 1957, the group meet at Gordon Moore's home at 1474 Alford Street in Los Altos. They realize that between them they posses all the expertise needed to make silicon transistors. They decide not to leave individually, but to leave as a group and go to a new company that wants to build silicon transistors. They also decide to keep up the appearance of working full-time at SSL while they look for backing. Gene Kleiner's father knows bankers who undertake to find companies to hire the team. Bud Coyle and Arthur Rock (yes, that Arthur Rock) are asked to help. On August 1st, Jim himself arrived at SSL for the first day of his apprenticeship. He took his IQ and personality test, and then was told Bob Noyce would be his device coach, Gordon Moore his diffusion coach, Jay Last his materials coach, and VicGrinich his circuits coach. Of course, he knew none of these people, and had no idea they had already decided to leave. Mid-August to mid-September 1957, Coyle and Rock, unable to find a company to hire the whole team suggest starting their own company. They arranged for the group to meet Sherman Fairchild, the founder and CEO of Fairchild Camera and Instrument. He offered the group $1.4M for 18 months with additional funding given progress. On 18th September 1957, each of the eight members of the group hands in individual resignation letters. Shockley wrote in his diary: "Wed 18 Sept — Group resigns." That's it. Fairchild On 19th September 1957, the group signed an agreement to form Fairchild Semiconductor Corporation (from now on, FSC) at 844 South Charleston Road. Jim considers this the birth certificate of Silicon Valley. March 1968, FSC announces its first silicon bipolar transistor, 6 months after leaving SSL, and 2 years after the formation of SSL. Meanwhile Shockley succeeds in producing 100 4-layer diodes per week, with initial uses in military applications. Meanwhile, the end of SSL. SSL succeeds in getting 4-layer diode production to 1000 devices per month. It has important military applications but volume is low. But Western Electric finally decides against using the device in major telephone switching, eliminating the major market. In April 1960, Beckman sells SSL for $1M, and Shockley takes a position as Professor of Engineering Science at Stanford. The business is finally formally closed in 1968. On 17th January 1959, Hoerni files for a patent on a planar process. Jim calls this "the single most important patent in the field, after Shockley's original invention of the bipolar transistor." A week later, on 23rd January, Noyce files patent for the integrated circuit, proposing to use the Hoerni process to fabricate multiple transistors on a single chip and then connect them into a functioning circuit. On 16th October, almost the last day possible, Fairchild Camera and Instrument exercises its option to buy out FSC. Each founder gets $300K (about $3M in today's dollars). That's a picture of them just after the buyout, from left to right: Gordon Moore, Sheldon Roberts, Gene Kleiner, Bob Noyce, Vic Grinich, Julie Blank, Jean Hoerni, and Jay Last. This is the only time, before or since, I've ever seen them in suits. Fairchildren 31st January 1961, Last and Hoerni leave FSC to form Amelco, a division of Teledyne. They are later joined by Roberts and Kleiner, dividing the original group of 8 into two groups of 4. Amelco creates a new paradigm for corporate formation with stock options for everyone and a flat organizational structure. FSC manufacturing manager Charlie Sporck leaves in 1967 as CEO of National Semiconductor (now part of TI) specializing in analog ICs. Noyce and Moore leave FSC in 1968 to form Intel. The microprocessor is invented by Ted Hoff in 1970, commercialized by Faggin and others, and the first products brought to market in 1971. Of course, Intel CPUs become the main force in the PC industry, and later the server industry. In 1972, FSC alums for two new major venture capital firms: Kleiner and Perkins start Kleiner Perkins (later with Caulfied and Byers too). Don Valentine, sales VP at FSC and then National, starts Sequoia Capital. These are still two of the most significant names in venture capital today. Plaque Unveiled Sculptures In addition to the official IEEE plaque, and the older California State Historical Marker that used to be in the ground in front of the Quonset hut, there are other new sculptures. The biggest diode and transistor (30 billion nm technology node?), and the biggest silicon atom ever: Watch the Dress Rehearsal The circumstances for photography and video at the actual event were not great, in an unfinished building, with one wall hastily finished and painted white to be used as a screen. Folding chairs. But there was a dress rehearsal at the Computer History Museum a couple of weeks ago. They made a video of Professor Gibbons, and it is up on YouTube (35 minutes). https://youtu.be/skebELGLNs0 Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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Is Ethernet Ready for the Automotive Market?
Consumer demand for advanced driver assistance and infotainment features are on the rise, opening up a new market for advanced Automotive systems. Automotive Ethernet allows to support more complex computing needs with the use of an Ethernet-based network for connections between in-vehicle electronic systems. The number of vehicles with automotive Ethernet began picking up over the last years, at which time BMW, Jaguar and Volkswagen had vehicles on the road with automotive Ethernet. From the PHY side, one-twisted-pair automotive Ethernet technology provides a single, centralized network backbone that simplifies the deployment of advanced features. The One-Pair Ether-Net Alliance, which supports the advancement of automotive Ethernet, reached more than 300 members earlier this year. Broadcom, for one, has observed that the use of Ethernet cabling versus the traditional vehicle harness wiring can make a major difference in the weight of the vehicle. Since the harness can comprise 50% of the labor costs of a vehicle, the ability to simplify that system while also supporting more advanced features is an attractive proposition. So automotive Ethernet is becoming the new communications backbone within the vehicle. The IEEE standards association is also working to add Time Sensitive Networking (TSN) features to the existing standards for 802.1 and 802.3 Ethernet to provide deterministic performance. Once completed, it will become practical to deploy standard Ethernet (with the TSN extensions) in real-time, mission critical applications. A major driving force behind the development of these new TSN standards is the emerging Automotive Ethernet market. The TSN new features include time synchronization and ingress policing which are essential requirements for almost all new automotive applications. Another new feature, scheduled traffic, will be required for the most critical ECU applications such as braking, etc. With the availability of the Cadence Verification IP for 1GbaseT and TSN, adopters can start working with these specifications immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure. The 1GBaseT and TSN provides a full-stack solution, including support to the PHY, MAC and TSN layers with comprehensive coverage model and protocol checkers. More details are available in Ethernet Verification IP portfolio . Thierry![]()
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Jobs: Farmer
Last summer, I took Fridays to write about technology museums. I planned to do a series on Fridays this summer on the odd jobs that I have done in my life before I started what you might consider my real career. But then Cadence Cloud took precedence. But now it is the dog-days of summer so I'm going to take a week of these, plus, for reasons too boring to cover, I need some lead time on next week's posts. One challenge with blogging is that there is a sort of announcement year. From late-July to early September it is summer and we don't make major announcements (and neither does anyone else). Then there is a flurry between mid-September and Thanksgiving. Then nothing until January. February seems to be quiet too, the only other time of year when I have a few days when I wonder what I'll write about. But I can leak to you all the major announcements Cadence has in the pipe for the next few weeks...crickets...crickets...ok, I'm back. Enjoy some weird jobs. Nursery Rhyme Career Advice There is an old rhyme that is supposed to predict what career you will have (or, since it is very old, for girls, what sort of man they will marry): Tinker, Tailor, Soldier, Sailor Rich Man, Poor Man, Beggar Man, Thief Well, I've done none of those. I suppose I was a "poor man" when I was a student, like most of us, but by any reasonable standard of destitution, we were not. And although I'm not enough of a "rich man" to have retired to my desert island, again I'm rich compared to most of the world, and even most of America. The US median income is $30K/year. Although, through a couple of random twists, I've ended up as a writer, I was an engineer (or engineering manager) for most of my career. But when I was in high school and a student, I did some interesting jobs far from where I ended up. I even worked in a chocolate factory—yes, Charlie in the Chocolate Factory is practically a documentary! Since not a lot happens in the semiconductor industry in the middle of summer, I thought I'd write about them. I learned a lot of skills I have never used again in these jobs. But, in a deeper sense, I learned how to be an employee: show up on time, get the job done, pitch in when crises arose. Plus, I learned to appreciate the social side of these jobs, mixing with people who I was not going to meet studying computer science. I've lived most of my life in the top-university/silicon-valley bubble. But these jobs let me see outside the bubble in a way I still appreciate today. Farmworker My first job was working on a friend's farm. Well, of course, it wasn't my friend who was the farmer, we were both 14 or 15. It was his father. In Britain, you are allowed to drive an agricultural tractor on the road at age 14 without any license, whereas the minimum age to drive a car was (and is) 17. So that was cool for a young teenager. But mostly I was driving tractors on the farm itself. It was summer, and we were harvesting wheat and barley. If you've never been beside one, let alone on one, a combine harvester is huge and insanely noisy. When the guy who drove it needed to check that the ears coming out the back were properly threshed, I'd get to drive it for a minute. It was like suddenly being handed the helm of a supertanker. I've never driven a bigger vehicle of any kind. But mostly my job was to drive up alongside with a trailer, and the combine would empty into the trailer. We did this without stopping, so I had to pace the combine so that the flow of grain all went in the trailer, starting at the back, and then ending up at the front (if you tried to do it the other way around, you couldn't see how close you were to having the stream of grain go off the back completely onto the ground). It would take somewhere between two and three full loads of the combine's tank to fill a trailer. We'd keep going after dark often. The combine could turn off one headlight, so you had a fighting chance of peering back into the darkness to see whether the grain was going into the trailer correctly. Then I'd take it back to the dryer/storage. This required a skill that is not obvious, especially if you have never tried it. How do you reverse a trailer? To go left, you have to first go right, so that the trailer gets going the correct way, but then you have to eventually go left to follow it. It would be nice to do it slowly, but the dryer chute that the trailer had to be emptied into was up a little rise, so you had to have enough speed to get up it. Otherwise, even a tractor would spin its wheels. So, at 14, I had to learn how to reverse a trailer at speed. Emptying the trailer just required the tractor hydraulics to tip the trailer up. The first year, the trailers required the tailgate to be opened manually, but a year later they were automatic, and would undo automatically once the trailer was sufficiently elevated. The other thing we were doing was bringing hay and straw bales into the barn, or delivering them to people in the area who had horses but no farm to grow their own hay. Straw bales weigh about 50 pounds (hay can be as much as 80 lbs) so tossing them around is an art (this was before the big round bales wrapped in plastic). I didn't even realize it was a skill until years later I was at a friend's house with a crowd of kids and adults. We helped the neighboring farmer unload a wagon of straw bales. The kids were barely strong enough to lift a bale, even in pairs, but the adults were equally clueless as to how to pick a bale off the wagon and bounce it on your thigh to get it up onto the stack of bales being constructed. "You've done this before. How'd you learn?" the farmer asked me. I told him about my teenage farming experience. It's not a skill I've needed in Silicon Valley! I did the job for a few weeks each summer for three years. The first year, I considered it just something fun to do during the summer, so I was completely surprised when my friend's father handed me an envelope with a few hundred pounds in it when he drove me to the station to go back home. I hadn't considered the possibility that I would be paid, or even thought too much about the fact that what I was doing had real value. Then, out of the blue, I had more money than I'd ever had before in my life. I never negotiated a rate, but I wasn't an idiot, so it wasn't a surprise when I got an envelope of cash the following two summers too. Since I had been working most days from 7am to 9pm (or even 11pm occasionally) I don't suppose my hourly rate was great (I was exploited child labor!) but I had a blast, learned a lot, and did things like drive a combine, that most people never have the opportunity to try. Being paid was icing on the cake. Urban Farming It turned out that my second job, my first real one where I had to go and get a National Insurance number (the equivalent of US Social Security number) was a sort of farming too. But urban farming. At that time in my life, I lived in Chatham (if you are a Navy brat, you get to live where all the dockyards are) and I got a job with Chatham County Council mowing lawns. In Britain, it is too cold in winter for grass to grow much, but summer is sunny and wet enough that they need a lot of attention, so they hire a bunch of students every summer to help out. As well as mowing the grass around the public housing, we had to clear various land owned by the council that was simply overgrown. The big problem with that, for me, is that I'm left-handed. Using a sickle (like the one on the old Soviet flag) has to be done either with your right hand or using your left hand backward. I expect they make left-handed sickles since they make left-handed versions of lots of things like scissors and golf clubs, but CCC didn't have any. So I had to manage as best I could and avoid hacking my leg. So that was my first encounter with the tax system (since I had previously been paid in envelopes of cash—yeah, I didn't pay tax) which was another eye-opener since tax and National Insurance contributions (like FICA in the US) were just abstract concepts I knew little about as a school pupil. Suddenly I was losing a good amount of real money. Tomorrow A printer and at a bakery with a baker who used to work on the Queen Mary going back and forth from Southampton to New York every week. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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升级到Allegro17.2-2016的10大理由之3:新的PAD编辑器——不只是一个新GUI
客户反馈是产品改善的关键 当您在理解Allegro 17.2-2016发行版的特点和优势时，我可以猜到您在想什么。“哦不，他们对我的工作环境做了什么破坏？”如果您已使用Allegro多年了，您就会理解我的意思。我们称之为零版本的发行版被用来建立数据库/改变架构，会导致某种程度上的升级中断。17.2有效结合了零版本和17.0 EAP(Early Access Program)版本内容，于是就有了17.2。多年前，当我们在考虑下一步需要开发什么时，我们首先就要从你们提交的客户变更请求(CCR)数据库中找答案。当我们在处理许多CCR的过程中，你们经常不喜欢我们立即回复 “Inactive” ，请不要认为这是 “忽略” 的意思，您们的CCR是我们规划产品的重要起点，“Padstack Overhaul”项目就是这种情况。在我们的数据库中，与焊盘相关的CCR数量最多，于是我们决定启动“Padstack Overhaul”这个项目。 项目从数据挖掘开始，我们评估了所有关于这个主题的100多份CCR，我们的应用团队同时开始开发新的用户界面。很遗憾地告诉您，与焊盘相关的旧代码将不再运行，这是我们发展产品过程中不得不做的牺牲。如果您决定不使用任何新功能，我们仍然保证您的16.6焊盘库与17.2兼容，但我认为您会喜欢我接下来分享的内容。 此次升级的关键主题是提高PCB设计效率和易用性。 您需求的： 更容易的新形状焊盘编辑 新的编辑器提供了许多新形状的焊盘，使复杂焊盘的设计变得更简单。有了这个版本，用户可以创建一些新形状的焊盘，例如甜甜圈形状、圆角矩形或倒角矩形。 （点击查看大图） 设计工程师也可以通过参数调整矩形角的类型，您可以创建墓碑形状的焊盘或仅是一个单角槽。这对于建库的好处在于可以立即实现，因为它们不再需要按形状画焊盘。 新的焊盘编辑器通过现代易用的图形界面创建焊盘，大大提高您的设计效率。向导似的工作方法可以轻松地定义焊盘及其所需属性。 您需求的： 内置禁止区 焊盘支持内置走线禁布区以及相邻层禁布区。对非金属化孔，可使用标准的禁布区形状，以及中间层可用的HDI过孔。也可以使用相邻层禁布区来挖空表面安装焊盘下的金属平面，以控制阻抗，但也可以用于机械埋/盲孔，以防止当钻头过冲时发生短路。对于相邻层禁布区，库管理员将生成几何图形，而PCB工程师可以应用属性来控制相邻图层的数量（最大为8）。 您要求的： 钻孔 大部分CAD系统都支持钻孔区域，我们所知道的是成品孔的尺寸，电镀后的尺寸。但之后，我们需要支持钻头尺寸和背钻尺寸。钻孔区域可用来指定您希望制造商使用的钻头。最可能使用的场景是为压接式连接器指定钻孔尺寸。 （点击查看大图） 背钻区域带动了背钻应用的主要软件功能升级，这是另一篇文章的主题了。使用这一区域可以指定钻头尺寸。这一信息被输出至NC Legend图表中。也可支持不常用的扩孔和锥孔结构。 您要求的： 复杂掩模方案 掩膜层可定义多种形状。多形状的掩膜方案必须被创建为.fsm文件，并被分配到掩膜焊盘层的定义中。以窗格掩膜方案为例，这种增强可以使之受益。 （点击查看大图） 您要求的： 增强的动态形状特性 我遇到的最常见的客户变更请求是关于这个增强特性的。因为每层都关联了动态图形，现在可以管理您的引脚/过孔的热焊盘/间距参数。与我们开发的创建约束区域的使用模型类似，您可以分级运用性能选项，包括外层、内部平面、内部信号和单层。常见的需求是关于控制元件引脚热焊盘触点的数量。 欢迎您的留言反馈！ 您是否有可分享的经验？ 您可以通过 PCB_marketing_China@cadence.com 联系我们，非常感谢您的关注以及宝贵意见。 相关视频：焊盘增强 https://youtu.be/jjjSXTBfvHI * 原创内容，转载请注明出处： https://community.cadence.com 相关阅读： 升级到Allegro17.2-2016的10大理由 Allegro最新技术 欢迎订阅“PCB、IC封装：设计与仿真分析”博客专栏， 或扫描二维码关注“CadencePCB和封装设计”微信公众号，更多精彩内容期待您的参与！ 联系我们：spb_china@cadence.com![]()
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CDNLive Taiwan – Cadence User Conference 2018
Date : August 14, 2018 Location : Hsinchu, Taiwan Agenda The Cadence User Conference, CDNLive Taiwan, on August 14, 2018, was a popular and successful event with over 1000 attendees. In addition, the Academic Network had their first ever Academic Track, from 1:30pm-5:00pm, moderated by Jess Yang from DSG. There were a total of 4 academic speakers that filled the conference room for the entire time, covering a variety of topics along the theme of AI Research and the Academic Network. The day started with Dr. Tian-Sheuan Chang , the Deputy Director of the National Chip Implementation Center and Professor of Electronics Engineering at the National Chiao Tung University, talking about AI Trends and CNN research & CIC collaboration with Cadence. He shared his experiences on a variety of efficient CNN hardware accelerator designs with resource constraints. The next speaker for the Academic Track was Dr. Jing-Jia Liou , Professor and Chair of Department of Electrical Engineering from National Tsing Hua University, who spoke about Optimizing Farneback Optical Flow Accelerators with HLS Flow. He shared how using Stratus High-Level Synthesis for teaching and fundamental research can make it convenient to evaluate architectures, both at module level and system level, and more efficient at RTL implementation for DSP algorithms. Dr. Yean-Ru Chen , former Cadence Application Engineer for JasperGold , now Assistant Professor in the Department of Electronics Engineering at National Cheng Kung University, hosted the third Academic Track session. She spoke about Formal Verification in the Academic Field, discussing her academic research, the advancements in formal verification technology, both theoretical concepts and application training, and the next steps in the coming years. The last session of the day was hosted by Weibin Ding, a Cadence Software Engineering Group Director of the Digital Implementation Group. He asked the question, “Can Deep Reinforcement Learning Produce Better Results on Digital Routing? and addressed the Challenges of Physical Implementation and Machine Learning Opportunities for Advanced Technology. Thank you to the many participants and attendees who made the event first Academic Track at CDNLive Taiwan a success. The Academic Network looks forward to many more years of participating in CDNLive, which brings together users, developers, and experts for networking and sharing of knowledge and best practices in the Electronic Design Automation industry.![]()
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Jobs: Printer, Baker, Chocolatier, Caver
Yesterday I covered my first job, as a farm-hand . Today I'll cover some other jobs that I've had that taught me a lot about different aspects of life. I do think everyone benefits from working in jobs that are outside the professional bubble, and I'm very glad for the experience. Printer At the high school I went to, we had an old letterpress press. Letterpress is the old-fashioned lead type where each letter is on a separate piece of metal. So I learned my way around those funny trays which hold the letters, where the divisions are all different sizes.The space allocated to a letter depended partly on how common it is, and partly on how big it is (physically). "e" is the biggest since it is the most common letter and not small like a comma. Ligatures like "ffi", which have their own piece of type, are the smallest. Eventually, the school's press ended up in a museum. Composing was the name given for putting the type together to make, say, the program for the school play. The letters had to be assembled into a sort of metal clamp from the case (you had to learn where the letters were, they are not labeled) and eventually they would be transferred to the frame in which the type was held for printing. The letters were backward (mirror image) and even today I can read mirror image type without difficulty. After the printing was finished, each piece of type had to be put back in its correct slot, known as dissing (short for distributing, I think). You could tell who was inexperienced since they would put the 'b's in the 'd's and vice versa (remember, type is mirror image). Between each row of letters would often be a strip of lead. If you've come across the term "leading" meaning the vertical space between lines in a word processor, then this is where that word comes from. You may have seen the phrase "don't bury the lede", meaning a journalist shouldn't put the most important part of the story in paragraph 17. The reason "lede" is spelled in a strange way is to avoid confusion with "lead" (the metal, not leadership) from the days of metal type. But even then, real-world printing was done mostly with offset lithography. Lithos is the Greek for stone, but actually, the printing was done on metal plates. Using a photographic process, the material to be printed would be transferred to the metal plate, leaving a waxy residue where the type should be printed. During printing, the plate would first be wet (with water). Then a roller would put ink on. But the ink would only stick where the water was not. Then the plate would be rolled over the paper and the ink and water transferred to the paper. Both water and ink would dry. This description makes it sound like a slow manual process, but the printing machine would run at several sheets of paper per second, and was almost completely automatic apart from refilling with paper and ink, and making small adjustments. Baker In Bath, I worked for an artisinal bakery, the Old Red House Bakery. That's it in the picture above, although it is now an architect's office, not a running bakery. That was back before artisinal bakeries were a thing. The oven was coal-fired, so it was hard-core artisinal. Our bread was good enough that some of the first batch had to be taken to the train station to get the train to London (100 miles away) to be taken to hotels that cared about their bread. The baker I worked with used to work on the Queen Mary liner, back in the days before air travel. I'd never thought about it before I worked there, but obviously, they had to bake their own bread. They couldn't just load up with a week's worth in Southampton to last them to New York, since it would be stale. The hours were the only thing bad about that job. On a normal day, we started at 5am (the master baker, who made the first dough, had been there since about 3am, but he left mid-morning). We finished around noon or 1pm. But Fridays we did a double shift. Having worked 5am to noon or so, we started again at 9pm and worked until about 6am making all the bread for everyone's weekend. There was a meme on Twitter recently, that "you are transported back to 1918, what job are you qualified for?". Well, I can still bake bread if I can get flour and yeast. That's more useful in 1918 than knowing how to design a NAND-gate or write a compiler. Baking bread isn't difficult, and if you have young kids, it is a great thing to do with them. Kneading bread, leaving it to rise and finding it has doubled in size, smelling it cooking, eating it when it is too hot to touch, these are all wonderful things to do with your children. If you are single, and want something unique to do on a date, bake bread together. Chocolatier I worked for Fry's Somerdale factory in Keynsham, near Bath, for three summers. Fry's was, by then, a subsidiary of Cadbury, and Cadbury would eventually end up as part of Kraft. The first year, I was on the night shift, which was four 10-hour shifts from 8pm to 7am. In a job like that, without going near a jet, you are permanently jet-lagged, working at night, and trying to have a social life when your friends are up and about at the weekends. My job was on a machine that packed Fry's Chocolate Cream, a type of confectionary that had been made for over a hundred years. After about two days, I could do every job around the machine, as we rotated, without thinking, so we would sit there for 10 hours chatting about whatever took our fancy. It was all men, women were not allowed to work night shifts in those days (at least in factories). The second and third years, I was in the warehouse, making up orders. It was a horrible job in comparison. It was during the day, so I had to work five days rather than four. But I had to think. I would pick up an order printout, then wander around the warehouse collecting what was on the order. Sometimes, I'd check other people's orders, since we double-checked every order. So in addition to not having the same social component, since we were all moving around all the time, I was on my feet the entire shift. In the middle of the third year, I got a job programming (see tomorrow's post) and I was rescued from factory work forever. Caver (Spelunker) Next I worked for a company called PGL Adventure Holidays in France. As you might guess from the name, they were actually an English company, and they ran holidays for English people (and also some groups from the Netherlands). The groups would go to the Ardèche and canoe down the river through the Ardèche Gorge for a week, and then go to Port Grimaud on the Mediterranean and sail for a week. It seems PGL still exist and even still take groups down the Ardèche gorge. I worked at the canoe part in the Ardèche. I'd never canoed. Since the Ardèche gorge was formed out of limestone, there were lots of caves too. At Cambridge, I'd been in the caving club (Americans call it "spelunking") so I knew my way around underground. So I was the caver and took groups caving, most of whom had never been underground before. The most interesting and fun one required swimming across an underground lake (very cold) and then going through several chambers decorated with stalactites (free hanging) and curtains (attached to the cave wall). It was beautiful, especially by candlelight. After the challenge of swimming through very cold water, people loved finding themselves next in a huge underground cavern with an austere beauty that nature had made over thousands of years. When we were not on the river, we all stayed in a big old house, Le Mas, at about the midpoint of the journey down the gorge. As well as taking groups down the caves, I would go down to the bottom of the gorge and meet groups coming down and help secure all the canoes and guide the groups up the path out of the gorge to the big old house. Just up the river from that point was a nudist camp. Generally, the group leaders told everyone when they went through that part of the gorge that they had to be nude too. Everyone knew it wasn't really true, but many of them did it anyway. One of the group leaders was Angus. I think his name was really Cameron, but since he was Scottish, his nickname was Angus. He had been the President of the Edinburgh University Canoe Club (EUCC). Since I had learned the basics of canoeing at PGL, when I got to Edinburgh, I joined the EUCC myself and learned how to canoe pretty well (actually white-water kayaking, but in Britain, we call all of it canoeing). I am even a "British Canoe Union Senior Instructor", or at least I was then. Graduate students were always in demand since British driving license regulations have an age limit of 17 for driving a car, but 21 for driving a minibus. Most undergraduates were too young to drive the minibuses. I think there may have been some additional regulations since we were also always pulling a trailer with all the canoes. Anyway, following in Angus/Cameron's footsteps, several years later, I too would become President of the Edinburgh University Canoe Club. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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Jobs: Fortran Programmer
Finally, the jobs theme gets technical. I had various programming jobs before I moved to the US to be a software engineer at VLSI Technology: Cambridge University Engineering Department, between high school and university. Pye-Unicam in Cambridge during the summer between 2nd and 3rd year at university, and during my third year (my final year since it was a 3-year degree course) and for about 6 months after graduating. Strathclyde University between undergraduate and postgraduate studies. Edinburgh University: University Demonstrator and then Computing Officer. Cambridge University Engineering Department My father's best friend in college became a lecturer at the Engineering Department at Cambridge University when he left the Royal Navy. His badge of honor is that he never did a PhD so he was an unusual lecturer since he was "Mr" not "Dr". Surgeons in Britain actually do the same thing. They used to be looked down on in the era before anesthetics as being little more than butchers, nothing like real physicians. So British surgeons today wear it with pride: when a doctor passes their surgery qualifications they drop the "Dr" and got back to "Mr'. Anyway, my father's best friend was also my godfather, so in a piece of god-nepotism he got me a job there as a programmer. I had learned to program when I was 14, which was most unusual then, still in the mainframe era, before even minicomputers. In that era, Cambridge University still had its own entrance exam (Oxford too) which you took in December, so most people would stay an extra term to do the exam, then have the rest of the year free until starting university. By the way, the physics entrance exam was famous for the compulsory question 1 which had about a dozen questions such as "how big must a hydrogen balloon be to lift a man", or "how near must a car get before you can distinguish its headlights separately". That was the whole question, you didn't get given any units (such as the density of hydrogen), you were expected to know rough numbers or estimate them. Anyway, my first job as a programmer was writing Fortran for the engineering department, either on the big Atlas time-sharing system or on the IBM 1130 in the basement. I was an okay programmer, especially given that I'd never taken any computer science courses (or even programming courses, it was years too early for schools to be doing that). In fact, I hadn't even got to university by then, of course. I was working on a project in mechanical computer-aided design. Capturing a designers intent for curves and curved surfaces is hard. The way a designer wants to specify them intuitively is often mathematically intractable, and things like Bêzier curves are easier to handle but hard for the designer to control. You probably know that, say, 5 points can be used to specify a 5th-degree polynomial, but usually it goes all over the place, and what you really want is a higher degree polynomial that is "smoother" but still goes through the points. We tried to use curvature (in the mathematical sense) to "fly" the line from guide point to guide point like flying a plane. The paper that came out of this work seems to be online still: Curvature Profiles for Plane Curves , my first published paper (although my godfather was the lead author). Pye-Unicam My first job as a programmer was working for Pye-Unicam (part of Philips) in Cambridge. They made spectrometers for chemical analysis. The optics were controlled by carefully shaped cams (hence the name of the company) that were so precise they had to be machined in a temperature controlled room. There were lots of expensive parts that my boss had worked out could be made much more cheaply out of sheet metal rather than being machined. My job was to create the program that took the description of the part, and produced the tape for the numerically controlled machine tool that punched the metal. Some companies used the same machine to make the sides of subway train carriages. We were taking a 6-foot square sheet of metal and making hundreds of parts that were only a few inches across. The last part of manufacturing there seems to have closed in 2014, and it is now the Pye Museum. I've programmed lots of different stuff since then, but there is nothing quite so visceral as seeing a bug in your program punched into a sheet of metal that then has to be discarded. Having a few pixels wrong on a display just isn't the same. I did that job between my 2nd and final years as an undergraduate, between studying mathematics, and computer science, which in those days was a one-year course. So at that point, I was still an autodidact, never having been taught how to program. It also carried on in the same job the most of the year after I graduated. Although at that company, I was programming, only a few of the machine tools were numerically-controlled. Most were created by skilled operators on lathes and drills. So I had one foot in the future, computer science, and one foot still in a real metal-beating factory. It turned out to be a sort of stepping-stone job, my last factory job and my first programming job. Strathclyde University Engineering Department Once I finished at Pye-Unicam, I still had several months before I was scheduled to go and work at PGL (as a caving instructor). On guy I had worked with at the Cambridge Engineering Department had gone to be a lecturer at Strathclyde University (in Glasgow). He persuaded me to come and work on some stuff there for 3 months, and I could live in his spare bedroom, so I went. The group where he worked was working on algorithms for numerically-controlled machine tools. Not the type I'd worked on at Pye-Unicam, which was punching sheet metal, but three-dimensional modeling. Think of the plastic agitator in the center of a top-loading washing machine, or the plastic molding around a car headlamp. These are complex to describe, and also complex to go from the description to the instructions to the machine tool to actually make the component. Part of the challenge is simply to move the tool to the right place, taking into account the size and shape of the cutting head. Another part is to avoid running into the part or the fixture holding it, by mistake. It was my first time living in Scotland. When you think of a broad Scottish accent, that is actually a Glasgow accent. The Edinburgh accent is quite different, despite the two cities being just 40 miles apart. Edinburgh University Computer Science Department I then made that 40-mile journey. Actually, I'm sure I went back to my parents house to pick up more of my stuff, 400 miles south in Bath. I used to be able to surprise people there by pointing out that I was going West when I went to Edinburgh, despite it being on the East coast of the country. Britain slopes to the West quite significantly. My father lives in Cornwall these days, in the fast South-West of England. I can surprise people there by pointing out that Land's End is not the most Westerly point of mainland Britain, Ardnamurchan Point in Scotland is even further West. As I said, Britain slopes to the West. After a short time at Edinburgh, I was offered a job as a "university demonstrator", which sounds like I should be marching in the streets. But it is a sort of cross between a teaching assistant and programmer for the department. It meant that I was being paid to do my PhD. Later, I got promoted to the equally oddly titled "computing officer" which was more like a cross between an assistant lecturer and a programmer. In fact I was in charge of a couple of courses on the Masters degree course. The most difficult to teach was the introductory programming course, because I'd been programming for so long that I couldn't remember what was difficult any more, whereas the Computer Networking course was easier to structure and teach. My PhD was actually in distributed file systems, which was a research topic in that era, although it is a standard part of any datacenter today. However, I also worked on a computer-aided design system for printed circuit boards. ESDL, the Edinburgh Structured Design Language, was my creation. In fact, today, to call it a design language is laughable. It was really a way of describing hierarchical netlists in text form. We then created tools to map gates into standard TTL logic components, manually put them on boards, and so on. I could probably have written all that up for my PhD if the file system thing didn't work out. I never really thought about it until writing these posts, but my programming jobs were all about computer aided design. Initially in mechanical design, sheet metal, numerically controlled milling machines, and so on. Then on to printed circuit boards, before coming to the US, joining VLSI Technology, and working on computer aided design of integrated circuits. Then I became a writer. But that's a story too far for today. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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The Price of Getting Rid of Traffic
I spend a lot of time commuting, as I generally drive around 80 miles a day to get to and from work. With that time in my car, I also spend a lot of time sitting in traffic. Now, I get a lot of reading done on these trips—thanks, recorded books!—but I also spend a lot of time thinking about all of the other people sharing the roads with me. Are we all in the same boat (so to speak)? Probably. And then I get to work and hear about autonomous vehicles (AVs), and the processors that will be required to make them. I immediately jump to the end of the scenario: what a dream, to be able to use an automated service to do the driving for me. Instead of subjecting myself to the dangers of the other crazy drivers on the road (certainly not me , I’m the perfect driver!) (ha), all of the vehicles will be all connected to each other, and complicated AI algorithms will manage the congestion, and poof! Traffic jams are gone. ADAS systems ensure that we’re all safe. My fellow commuters and I will be able to work, read, sleep, practice the oboe, write poetry, knit blankets for our armadillos, meditate, do crossword puzzles, watch movies, make papier-mâché sculptures—all from the safety and smooth sailing of our AVs. We could play chess, too! But what is the real price of getting rid of traffic? Smarter people than I are only just starting to tackle this question. To put it mildly, there are vastly differing projected outcomes. San Cleveyorkucson Let’s consider a fictional city, let’s call it San Cleveyorkucson, where the only transportation is AVs. (We’ll assume that the challenges of having mixed transportation has already been overcome, and now only AVs are on the roads.) In this city, there are tech centers, industrial areas, service areas, hospitals, schools, maybe even a university or college; there is also low-income housing, luxury neighborhoods, and those in-between. There are public transportation and single occupancy robo-taxis; there are autonomous delivery vehicles and drones and shared AVs. San Cleveyorkucson First, let’s think about the design of the city itself. All of the current parking garages, all the fuel stations, all the auto service centers, even all the places that sell cars—all of this space will become space that can be utilized for something else. Imagine the urban gardens, the public spaces that can take the place of some of this current concrete. Streets themselves could become narrower and can be “re-programmed” over the course of the day to accommodate traffic flows, events, pedestrians, emergency vehicles. Yay, no more traffic! The AVs are managed such that even when there are more vehicles on the road, they are managed such that speed is still maintained, with no hindrance to getting from site A to site B. Semis and other freight vehicles run at night, further reducing traffic and increasing safety. The elderly and disabled will have a new sense of mobility that will solve so many problems. Sprawl So what is to prevent the Smith family from moving way outside of the city limits? Mr. and Mrs. Smith can work during their hours-long AV commute, so what’s the problem with them moving? One problem is that of urban sprawl. City planners, the guardians of natural habitats and productive agricultural grounds, tend to frown on this. The environmental ramifications alone are problematic at best (unless these AVs are electric, powered by solar farms). San Cleveyorkucson could experience cancerous growth beyond the reaches of the city borders and into that wild beyond. Urban blight may appear as all the upwardly-mobile workforce moves away from the city, relying on AVs to get them to and from work. Suburbs of Las Vegas, an example of urban sprawl In addition, my city planner friend also points out that: “… over the very long term, sprawl makes it difficult to generate the revenue needed to maintain the infrastructure. A lot of our current problems with roads, bridges, waterlines, etc. can be attributed to decades of development at densities that are not fiscally sustainable.” This is a good point, one that I hadn’t considered before. Interestingly, however, in this article , another model comes to mind. “The emergence of AVs helpfully coincides with a change in the structure of cities, says Shlomo Angel, an urban-studies expert at New York University. He argues that the monocentric model, with a center surrounded by suburbs, is a thing of the past. In many large American and European cities, jobs are moving from downtown to the periphery, and workers increasingly commute from one suburb to another, rather than to and from the center. His analysis shows that 75% of jobs in a typical American city are outside the urban center. In European and Asian cities with dense public-transport networks this decentralization is easier to cope with, but retrofitting the necessary infrastructure onto American cities would be too expensive. “American cities need door-to-door transport systems to get to work, and driverless cars will play this role beautifully,” says Mr. Angel. Maybe the problem of sprawl will become its own solution. Public Transportation Another problem may arise about public transportation. For a city to be truly healthy, all income levels must be able to live and work there. For the lower income levels, using AVs regularly may not be an economic reality and they must rely on public transit. That said, it could be that city managers may determine that due to the ubiquity of AVs, they no longer need to fund busses or subways or trolleys. According to the article cited above: “A study by UC Davis found that among Uber and Lyft riders in America, bus use fell by 6% and light-rail use by 3%. … This might discourage further investment in public transport, which in turn could create more “transit deserts” where large numbers of people (typically the poor and the elderly) depend on public transport but get an inadequate service.” De-funding the “luxury” of transportation is the first step in making people with low incomes move away from this utopia of San Cleveyorkucson. And once they start leaving, you have problems with gentrification: the poor leave, the wealthy move in to displace them, and the economic structure of the city starts to cave in on itself, leading teachers and police officers and service members and other middle-income levels to not be able to afford to live there. (See: San Francisco, Hong Kong, New York, Los Angeles, even my hometown of Santa Cruz…) It could be that a public AV fleet will solve the public transportation problem, however. Pricing models for AVs that cost the same as a BART or light rail or bus ride could make public transportation as it currently exists obsolete. Why even bother maintaining the tracks when the same number of commuters can be accommodated by ride-sharing AVs? It will become a challenge in building the proper infrastructure and developing pricing models thoughtfully and with this kind of growth in mind. The Answers to These Questions Sorry to get your hopes up, I don’t have the answers; I’m by no means an expert. Working at Cadence, where we build the tools that enable the chips/boards/systems that will build the future, I can’t help but try to follow the ramifications of our work on the rest of the world. Better processors, better testing, better verification, better simulation, better emulation—these are all required for us to get to true level-5 autonomy in transportation, and we at Cadence are no doubt a part of the AV revolution. I just want to be sure that those enabling the AV future will follow the logical steps to where this new technology will take us. —Meera Things I Read for This Post https://www.economist.com/special-report/2018/03/01/a-chance-to-transform-urban-planning An exceptionally interesting article in a special report on autonomous driving; the entire series is well-researched and thoughtful. https://www.facebook.com/meeracollier/posts/10214426068418739 I posed the question to the people following me on Facebook and got some fantastic and interesting replies; thanks to everyone who spent some time hashing this over with me! Take a look, if you’re interested in the comments that were added to my informal poll. And add your thoughts, if you’re so inclined!![]()
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Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 1
In this week's Whiteboard Wednesday, Tom Hackett explains neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here: https://ip.cadence.com/uploads/1213/neural-network-calculator-xlxs-zip https://youtu.be/YAaC94Ke2Ls![]()
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Preview of Electronic Design Process Symposium 2018
It is nearly EDPS time again when the dolphin logo comes out, somewhat incongruously now that EDPS is held in Milpitas, not Monterey. EDPS is the Electronic Design Process Symposium. It is a relatively small conference, but it always seems to be covering the most important topics each year. The conference is September 13th and 14th at the SEMI headquarters in Milpitas. See the end of this post for full details and how to register. Keynotes Chris Rowen The opening keynote is by Chris Rowen, emeritus CTO of the Cadence IP group, and now the CEO of BabbleLabs, which you might guess from the name has something to do with speech and speech recognition. His keynote is titled Deep Learning Revolution—From Theory for Impact . After many years of academic obscurity, deep learning has suddenly become one of the most important and transformative innovations in computing today. Spectacular successes in computer vision, speech and other pattern recognition tasks are capturing the attention of algorithm designers software developers and system architects across many applications. This talk outlines the key ideas of deep learning, explores the systematic improvements in accuracy in perception and recognition tasks, and looks at the rapid changes in underlying computer architectures, in application development methods, and in human-machine interfaces. Andrew Kahng Andrew gets the soporific keynote right after lunch on the first day. He is Professor of CSE and ECE at UC San Diego. His talk is titled Driving, Driven, Along for the Ride: Evolution of EDA, Manufacturing, and Design . The relationships among EDA, Manufacturing and Design have evolved in many ways, as a consequence of various macro trends, over the past decades. The transition from IDM to fabless-foundry. The challenges of classic Moore's-Law density and cost scaling. The inexorable growth of variability, margins and design/signoff complexity. The visions of DFM (and MAD, DAM) modulating into DTCO -- amidst severe industry consolidation. The uncertain future of beyond-Moore / beyond-CMOS. Despite so many compelling forces, the three technology communities -- EDA, Manufacturing (and Test) and Design remain remarkably separated, with relatively arms-length interactions. This talk will try to explore some reasons behind this, and how some of the relationships and roles (driving, driven, along for the ride) might change in the future. Jim Hogan and Amit Gupta The dinner keynote is not really a keynote. The ESD Alliance is mounting the next of their "crossing the chasm" evenings with Jim Hogan. This time he will interview Amit Gupta on his recipe for success (he has two successful EDA exits, ADA and Solido). It so happens, I interviewed Amit on just this topic just before I joined Cadence, and so I'll have more details on that tomorrow. Simon Johnson Simon is a senior principal engineer at Intel. He kicks off the second day of the symposium with a keynote that is titled Hardware-Based Security . Sessions Thursday Innovative Design: Techniques. Despite the innocuous session title, this appears to be largely about machine learning in EDA, with Patrick Groenveld of Cadence/Stanford, Joonyoung Kim of NXL, Rohit Sherma of Fairpath, and Jai Kumar of Intel. Smart Manufacturing: Talks are scheduled by Don Draper (no, not the Mad Men one), Chris Bailey of University of Greenwich (London), Tom Salmon of SEMI, Wilfred Bain of NextFlex, Matt Knowles of Mentor, and Dave Armstrong of Advantest. System Reliability for ADAS, 5G, AI and Photonics: with Di Liang of HP Labs, Amisha Sheth of Intel, Ritesh Tyagi of Intel, and Norman Chang of ANSYS. Friday Cyber Security: with Alessandra Nardi of Cadence, Huafeng Yu of Boeing Research Technology, and Naresh Sheel of Intel. After lunch, there will be a panel on Introduction to Blockchain . The symposium will then wrap up early enough that the Friday afternoon traffic shouldn't be too bad (good luck with that). Details The conference will be held at SEMI Headquarters which are at 673 South Milpitas Boulevard in Milpitas. Both days start at 8am with breakfast, registration, and networking. The symposium proper starts at 8.45am. The first day runs all the way through dinner, the second day finishes mid-afternoon with a wrap-up after the panel session. Full details on the EDPS webpage . Registration is handled vie Eventbrite . I'll see you there. Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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What's For Breakfast? Video Preview August 27th to 31st 2018
https://youtu.be/hxqDm1EAS7M \ Coming from the flagpoles in front of building 5 (camera Sean) Monday: PCAST: President's Council of Advisors on Science and Technology Tuesday: DARPA's Electronics Resurgence Initiative Wednesday: ERI: CHIPS and Chiplets Thursday: ERI: OpenROAD Friday: ERI: Hardware Security Workshop www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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Crossing the Chasm: Hogan Interviews Amit Gupta
The ESD Alliance will host another of its startup evenings with Jim Hogan, entitled Crossing the Chasm: Building a Startup to a Successful Exit . It is actually the evening in the middle of EDPS, the Electronic Design Process Symposium, as a sort of dinner keynote. And yes, dinner is provided. Yesterday I previewed EDPS . As usual, the ESD Alliance evening features Jim Hogan, this time in conversation with Amit Gupta. He was the co-founder of Solido Design Automation. Since his company was acquired by Mentor, I think we can say he succeeded in doing just that. Even more so, since he was also the founding CEO of Analog Design Automation (ADA) which Synopsys acquired in 2004. The event will be on Thursday, September 13th, from 6-9pm at the SEMI Headquarters in Milpitas. Note: if you think SEMI is still on Montague Expressway, they moved to Milpitas. As it happens, I interviewed Amit on just this topic myself, a few years ago. The challenge for an EDA startup is not to get to $1M, since everyone has some friends. But getting from there to $5M to $10M to $20M is really hard. When I talked to Amit, he had broken his advice down into a series of lists. The first list for the early startup phase, the second list to get across the chasm to proliferation, and then finally what to do after that (basically decide if and how you want to exit). I assume you have read Geoffrey Moore's book Crossing the Chasm . If not, then rush out and buy it immediately. The key point is that the reason early adopters buy a product is not the same as what will get the mainstream market to buy it. You need a more complete product. For example, early adopters will do things like writing their own technology files. The mainstream expects the foundry to provide them. Before the Chasm Find out what the customer pain points are from technology enthusiasts: of course, this means that you need to have done a good job of networking to know who have access to the technology enthusiasts who you trust. Validate customer pain points across many technology enthusiasts in many different companies. Don't design a solution for only one company/enthusiast. This is perhaps the most important step of all. I would say that technology startups in general, and EDA startups in particular, fail most often by developing interesting technology without validating that it solves a problem that people are prepared to pay real money for. The analogy I like is that you need to develop "penicillin, not "multivitamins". Ensure that there is a large enough market if the product is successful. I have a phrase "Intel only needs one copy" that describes products that are only used occasionally in the design cycle. These are very difficult to proliferate into a sizable business. Ensure that there is alignment between technology enthusiasts, company pain points, and what companies will pay for. Avoid science projects for technology enthusiasts. I guess we could call that "Intel doesn't need any copies at all". Figure out a business model to capture the value being delivered (floating licenses, site license, royalty...). If you are developing an EDA tool, the answer had better be some sort of time-based floating license. You can dream up your own license model, but at the very least it will slow the sales cycle if not kill the deal. It is like opening a restaurant and charging people by the hour instead of by the dishes they order. It's not totally stupid, it's just not the way that customers are used to. With 1-5 raise any investment needed to execute. Today, VCs expect some level of development to a minimal product with some key customers prepared to say they will buy it. Developing software with laptops and cloud doesn't require much investment so you should be able to get started with sweat equity. Innovate to solve customer pain points with 10X differentiation from competition, especially from the big guys (yeah, like Cadence) who can plausibly say they will have it next year if it is just 2-3X better. EDA customers are very risk-averse, and buying from a startup is risky, by definition. But semiconductor nodes are ruthless, and you can't ignore new problems. The only question is will you go to a startup or will your primary EDA supplier come through with what you need? Hire a product development team capable of delivering product with the customer in the loop. Amit's secret with both ADA and Solido was to do this in Saskatoon. The government pays a lot of the cost, and although it may be hard to persuade people to move there (it has Canadian winters), the people already there are not keen to move away. Develop minimum viable product (MVP). Iterate until successfully deployed minimum viable product with technology enthusiasts (early adopters) finding product-market fit. Establish needed partnerships with big EDA companies to integrate the product into customer flows (Cadence Connections, Synopsys InSync, Mentor OpenDoor, etc). This will also require customer references. Survive any market downturns, there will probably be at least one period of weakness/trauma. Execute fast enough that competition doesn't catch up, the market window doesn't pass (although being too early is often more of a problem), and you don't run out of money. Fail fast on stuff that isn't going to work out. Don't burn up your cash. Close first purchase orders. The only validation that counts. Crossing the Chasm If and only if (aka iff for mathematicians) you successfully complete all these steps do you have a shot at crossing the chasm. Then you can read Geoffrey Moore's next book Inside the Tornado (which uses Synopsys in early Design Compiler days as one example). This is the point at which you throw gasoline on the fire. In my opinion, it is the critical decision point in an EDA startup (and many other types): when do you ramp sales? Too early and you run out of money paying a sales force who cannot sell the immature product. Too late and...this never happens. I have only had one experience of being "inside the tornado" and that was at Ambit. One year we did $840K in revenue. The next year we did $10.8M. Read that story in my recent blog post on the 20th anniversary of our acquisition by Cadence . Amit's advice was that you need to: Mature the whole product solution for deployment to a larger mainstream audience (proliferation). This probably will require other partners, such as foundries or other tools in the design flow. Develop a sales recipe for short evaluations at a high success rate. Aim for 90 days from discovery to close, not 9 months Build out the company: engineering, AEs, marketing, sales, G&A Deploy and support the larger customer base Grow How to Handle Success Then in the third phase, Amid has a very short list: Be acquired, probably by Mentor, Cadence, or Synopsys. IPO...this never happens, especially post Sarbanes-Oxley which requires the company to be much larger than in the past. Grow profitably, generating cash (Denali showed it can be done for many years before Cadence made them an offer they could not refuse). More Rules For the biggest picture of all, the whole company, there are also a few rules. First, never take more than $10M in investment ($5M is better) or it will be really hard to sell in a way that makes everyone whole (carve-out and cram-down are not good words). Patents are important, research shows $300-900K per patent in additional exit valuation over and above forward revenue multiple. But don't do too many since they are expensive to file and expensive to maintain. Market the company too, not just the product. Sell the sizzle as well as the steak. ESD Alliance Evening Once again, the event will be held on Thursday, September 13th from 6-9pm at the SEMI Headquarters in Milpitas. If you want to come, then register . If you are registered for EDPS then this is included and I don't think you need to register a second time. Date: Time: Thursday, September 13, 2018 Dinner: 6:00 pm – 7:00 pm Amit and Jim: 7:00 pm – 9:00 pm Location: SEMI 673 S. Milpitas Blvd Milpitas, CA 95035 Cost: ESD Alliance Members: Free Registered EDPS Attendees: Included Non-Members and Guests: $50 Sign up for Sunday Brunch, the weekly Breakfast Bytes email.![]()
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CDNLive日本：第四次工业革命与三维世界
7 月 20 日 在CDNLive日本站，Cadence公司资深副总裁、兼定制IC芯片和 PCB事业部总经理Tom Beckley发表了主题演讲 “实现第四次工业革命（工业4.0）” 。同时，他宣布了 Sigrity 2018的最新版本 正 式发布，该版本是Sigrity电源和信号完整性分析工具的最新版本，融合了大量的机械设计和rigid-flex支持功能，帮助用户解决日益复杂的多板系统问题。 其后，Brad Griffin(Cadence Product Management Group Director)发表演讲 “攻克多板系统的仿真难题” ，就Sigrity 2018最新版的更多细节内容做出了详细解释。 Tom Beckley 想象一下反乌托邦式的未来：我们所有的工作都被机器人接管，Tom Beckley的演讲也被机器人Pepper所取代——Pepper欢迎大家来到CDNLive日本，然后请Tom走上台；当Tom开始谈论数据时，Pepper则温顺地站在一旁… 这就是机器人的时代。即使是电子行业之外的人也已经意识到大数据和人工智能领域正在引领着一场变革。大量的图表表明2020年我们将拥有40亿的互联人口以及250亿个嵌入式智能系统，这一切将产生50万亿千兆字节的数据。 你可能听过 “数据是新时代的石油” 这一说法。但正如一桶原油在经过全面处理之前无法真正发挥作用，数据也需要进行处理。 第一次工业革命始于18世纪晚期的英格兰北部，最初使用水力而后改用蒸汽来自动化钢铁和纺织业。 第二次工业革命是以电力和内燃机为“驱动力”的大规模生产的时代。石油作为汽车、卡车、飞机和船舶的燃料，成为了经济与社会的命脉。 第三次工业革命则是计算机及信息技术革命，它横跨了很长一段时间，从第一台计算机发明到大型主机、PC、直到互联网的出现。然而我却认为这场大变革开始于这一天：2007年1月9日，一名男子打电话给一位名叫Hannah Zhang的星巴克咖啡师，并订购了4,000份拿铁。这名男子正是Steve Jobs，而那是第一次iPhone通话（外部测试）。从此，智能手机改变了一切。 它改变了所有相关公司的价值。第一次和第二次工业革命以原料为主，尤以石油为重。1975年，顶级公司都是石油公司或石油消费公司： 埃克森美孚 通用汽车 福特汽车 壳牌石油 美孚石油 雪弗龙集团 而今天，当我们开始经历第四次工业革命时，我们心中的顶级公司却是： 苹果公司 谷歌公司 阿里巴巴 腾讯 百度 微软 亚马逊 Facebook（脸书） 三星 英特尔 数据，作为新时代的石油，已经掌控了我们的股市、经济与社会。 那么未来将如何发展？ 机器人技术（“Hi Pepper”）、人工智能、纳米技术、量子计算、物联网、自动驾驶汽车和生物技术，这些领域（主要）都是利用大量数据再将其应用于训练新的算法。我们不再像1999年那样埋头编程; 我们正在训练神经网络完成我们甚至都不知道如何编程的事情。 一个取得惊人进展的领域是自动驾驶汽车。DARPA（美国国防部高级研究计划局）在2004年开展了第一次挑战。当年的无人车在120英里的赛道上最多只能自动行驶7.3英里。 但是到了2005年，技术发展的速度令人难以置信。200万美元的奖金和全新的赛道（包括100个弯道、三个隧道和最后一段一侧陡坡一侧悬崖的通道）吸引了23位决赛选手；除了一位选手之外，其他选手都比前一年7.3英里的获胜成绩更进一步， 更有五辆车完成了全部132英里的路程。 工业4.0为IC芯片和系统公司提供了巨大的商机和风险： 传感器、电气、机械、射频、软件以及芯片融合在一起；机器学习正在改变系统（特别是涉及视觉的系统）的组装方式。传统的“系统”公司界限正在消失——OEM的界限变得模糊：Alphabet（谷歌）在制造汽车; 苹果和华为在设计手机芯片而不再从半导体公司购买；硅谷的创业公司已被 “人工智能” 这个词语淹没。5G将改变更多我们认知领域里的界限。 而机遇也正在从风险中酝酿：正如Mentor Graphics 的CEO Wally Rhines在DARPA ERI活动的演讲中所言，“许多深度学习的芯片公司将无法生存… 但与此同时，它们都需要EDA软件。” 诚然，但是比起任何时候，即使像Cadence这样的公司也无法单独实现一切，“系统设计实现”（SDE）需要各个垂直行业的不同合作伙伴。 （点击查看大图） 在机器人Pepper回到台上结束主题演讲之前，Tom提到了一些关于机器人的有趣数据。下表显示了每100名工人对应的机器人数量。然而最令人惊讶的数据则是：日本自2015年推出“新机器人战略”以来，他们使用的机器人已经节省了25％的劳动力（落后于韩国和新加坡），但他们却出口了75%所制造的机器人，占日本出口总量的11％。2022年，机器人预计将拥有价值250亿美元的商机，大约是价值500亿美元智能手机市场的一半。 （点击查看大图） 是时候让机器人Pepper为日本出口做出自己的贡献了。 Brad Griffin 电源和信号完整性的挑战之一，实际上也是对于任何形式的完整系统分析挑战之一，都是电源和信号不遵从技术和组织结构的边界。在某种复杂的实际情况下，信号可能必须经过芯片、复杂封装、电路板、电缆连接器、双绞线，再通过另一个连接器，经过电路板而到达另一个封装从而进入接收芯片。“不遵从技术边界”是指该过程需要很多不同的技术：硅、封装、电路板、3D连接器、电缆。“不遵从组织结构边界”则是指这两个芯片可能需由不同的设计团队（甚至是不同的公司，尤其对于存储器而言）进行设计。电路板可以由不同的设计团队完成，连接器和电缆可以直接购买。但是谁会对系统的完整性负责？ 谁又能将所有不同的分析方法汇集在一起来实际完成任务？ 对于芯片运行速度越来越快、封装技术越来越复杂、功耗越来越低的情况… 以及人力更少、时间更紧的进度表而言，我相信你一定大有可言。 （点击查看大图） 而对于能将所有分析技术集成在一起来解决实际问题的答案则是Cadence Sigrity 2018最新版及其3D workbench技术。该版本将电气和3D机械结构集成到系统完整性流程中。上图给出了需要分析的结构类型的复杂性。本节开头的GIF显示了复杂的多位插头和插槽的复杂程度。 （点击查看大图） Brad举了一个例子：相机及其外壳。 底座的一部分带有镜头，一部分带有电缆。 （点击查看大图） 如上图，相机由两块电路板组成：连接器、网络接口，并假设有一个由2或3个非常薄的尺寸相同的相连芯片组成的CMOS图像传感器（当今CMOS图像传感器的光由背面薄薄的芯片透过，就像你试图从背面看电视机一样）。 （点击查看大图） 我们想要分析的问题是相机如何与通风孔协作。系统完整性的挑战在于任何因素都会影响其它一切。如果孔太大，设计会降温，但EMI可能是不可接受的。温度受功率影响，但功率也受温度影响，信号完整性则受二者同时影响。 新闻发布中的重点内容如下： 热，信号完整性，电源完整性，ESD，EMI分析 使用合并连接器和PCB的3D模型对多板系统进行高级精度仿真 考虑电缆和连接器的系统级影响，优化PCB的信号和电源完整性 更多关于Cadence Sigrity 2018最新版及其3D workbench技术的新闻发布内容，可点击英文原文查看： Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 或访问Cadence官方网站查看 Sigiry产品最新详细信息 。 * 原创内容，转载请注明出处： https://community.cadence.com 欢迎订阅“PCB、IC封装：设计与仿真分析”博客专栏， 或扫描二维码关注“CadencePCB和封装设计”微信公众号，更多精彩内容期待您的参与！ 联系我们：spb_china@cadence.com![]()
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