The biggest yearly event in electronic design automation (EDA) is due to take over San Francisco next week, together, apparently, with the Apple developer community, to take over the Moscone Convention Center. This is the first DAC at which all three big EDA vendors will talk about their continuum of verification engines. I will continue to point out (until being stopped) that Cadence was the first vendor to announce its offering in this space – the System Development Suite – at least three years ahead of everybody else back in 2011. For some more background, there is a good article by Jim Hogan called, "“ Hogan proposes Continuum Of Verification Engines (COVE) concept. ” And how far we have come! What was introduced as a set of connected engines – virtual, RTL simulation, emulation, and FPGA-based prototyping – today also includes JasperGold formal verification as well as Stratus High-Level Synthesis (HLS) as core engines. Across them we support Verification IP, Indago Debug Platform, Incisive vManager planning and management solution, as well as Perspec System Verifier for software-driven verification. In addition, there are six solutions spanning the System Development Suite, from TLM design and verification centered around Stratus HLS and Incisive TLM-driven verification to metric-driven verification, ARM-based SoC development, low power and mixed signal, and functional safety (focused today on automotive). Clearly, the System Development Suite is already going well beyond the COVE concepts I referenced above. Below I've assembled an overview of some of the key verification sessions at DAC. Here are some of my favorites: The luncheon panel on "Smarter Verification" on Monday will give unique insights into software-driven and scenario-driven approaches to make verification smarter. Jim Hogan will open it - always fun and interesting - and we have really interesting speakers from AMD (Alex Starr), Qualcomm (Sanjay Gupta), Breker (Adnan Hamid) and, of course, our very own Ziv Binyamini, discussing with Brian Fuller the state-of-the-art approaches and trends. I am always keen to hear direct customer experiences. There will be plenty at the Cadence Theater in our booth (#3515): AMD, NVIDIA, Netspeed, and ARM will talk about emulation, including hybrids with virtual platforms to accelerate OS boot, as well as low power Oskitech and Imagination will talk about formal verification approaches Socionext and Methods2Business will outline their experiences with high-level synthesis Broadcom and AMD will focus on low power with RTL simulation and emulation JB Systems and DINI will focus on trends in FPGA-based prototyping Allegro Microsystems will talk automotive with a focus on functional safety. We will also present in the Automotive Pavilion. National Instruments and Methods2Business will touch on some of the key trends - connecting test and verification, as well as raising verification abstractions with TLM-based design flows Last but not least, yours truly will present on verification solutions for ARM-based design. I will also give this presentation at the ARM booth on Tuesday at 2:45pm. If you can make it on Sunday, Steve Carlson will present at a workshop on thermal and low power This year we will have an Experts Bar - the verification topics time slots are below and, of course, we are giving in-depth demos in the suite, for which you can sign up See you at DAC! Best, Frank Schirrmeister Panels Monday, June 08, 2015, Room 101 IP TRACK PANEL: Um, How Do We Know the Design Will Work? The IP Implementation Panel 2:30 PM - 03:00 PM Typical implementation challenges that companies are facing today include IP selection, the verification process, and technology integration – all crucial phases to an IP-based design. But consider some equally crucial challenges. For instance chip size; billion transistor chips affect tool capacity, runtime, memory, and yield. And what about these formerly separate, but now acutely connected, issues such as overall timing, signoff, variability, test, binning, performance, and yield mesh? These issues in combination can greatly complicate the design, implementation, and manufacturing process.This panel of industry experts will discuss the pitfalls of these difficult challenges and explore some potential solutions. They will share from their own unique perspectives various techniques and methodologies used to achieve successful IP-based SoC design implementation. Panelists: Darren Jones, Xilinx; Lawrence Loh, Cadence; Sean Smith, Soft Machines Moderator: Ed Sperling Details : http://www2.dac.com/events/eventdetails.aspx?id=190-5 Tuesday, June 09, 2015, Room 101 IP TRACK PANEL: Key Challenges of Verification and Validation of Modern Semiconductor IP 11:30 AM - 12:00 PM This panel of respected experts will discuss the key challenges of verification and validation of modern semiconductor devices. Topic areas will include verification IP, reusable testbenches, best practices for using assertions, hardware prototyping, accelerated models, and emulation. The theme of the panel will be related to how these techniques can be best applied in today’s IP-based design methodologies. Panelists: Tom Anderson, Breker; Toshio Nakama, S2C, Inc.; Bernie Delay, Synopsys; Raik Brinkmann – OneSpin; Frank Schirrmeister, Cadence Moderator: Brian Fuller Details : http://www2.dac.com/events/eventdetails.aspx?id=190-16 Tuesday, June 09, 2015, ChipEstimate Booth PANEL: “How to Address the Challenges of IP Configuration, SoC Integration and Performance Verification” 3:00 PM - 4:00 PM Speakers from ARM, Cadence, and Samsung Customers at Cadence DAC Theatre (at Cadence booth) Monday Company Session 10:00 AM Oskitech Is End-to-End Formal Complete? 10:30 AM AMD Experiences with SoC deployment of hardware emulation based power intent modeling 1:30 PM Allegro MicroSystems Applying ISO26262 Functional Safety Simulation 3:00 PM Broadcom Low Power Verification USING CPF/IEEE 1801 and Application of Formal Verification at Chip Level 3:30 PM NVIDIA Delivering High Quality Denver IP Utilizing IP Acceleration 4:30 PM National Instruments Pre and Post Silicon Verification - The Best of Both Worlds 5:30 PM ST Microelectronics Enabling Verification of Complex System Scenarios Using Perspec™ System Verifier Tuesday Company Session 10:30 AM ARM Reducing Time to Point of Interest with Accelerated OS Boot 11:30 AM Methods2Business Leveraging a SystemC-Based Design Flow to Realize ULP 802.11ah Wi-Fi™ Hardware and Software 12:00 PM Imagination The Ten Myths About Formal 12:30 PM Netspeed Using Palladium Platform to Exhaustively Verify a Configurable Coherent NoC IP 1:00 PM Broadcom How to Bring Formal to Main Stream 5:00 PM Socionext High-Level Synthesis: A Winning Technology Wednesday Company Session 12:00 PM JB Systems Case Studies for Successful FPGA Based Prototyping 1:00 PM Cadence/ARM Verification Solutions for ARM® Based Design 2:30 PM Dini Group Performance AND Productivity in FPGA Based Prototyping Expert Bar (at Cadence booth) Monday Topic 10:00am - 12:00pm HW-assisted Verification Featuring Protium™ and Palladium® Platforms 2:00pm - 4:00pm Formal Verification Featuring JasperGOLD® Apps 4:00pm - 6:00pm High-level Synthesis with Stratus™ HLS Verification Debug and Root-Cause Analysis Featuring Indago™ Debug Platform 6:00pm - 7:00pm Software-driven SoC Verification Featuring Perspec™ System Verifier Cadence® Verification and Implementation Solutions for ARM® Based Designs Automotive Featuring ADAS and Safety Tuesday Topic 10:00am - 12:00pm High-level Synthesis with Stratus™ HLS 12:00pm - 2:00pm Software-driven SoC Verification Featuring Perspec™ System Verifier HW-assisted Verification Featuring Protium™ and Palladium® Platforms 2:00pm - 4:00pm Formal Verification Featuring JasperGOLD® Apps 4:00pm - 6:00pm Simplify SoC Verification with VIP Verification Debug and Root-Cause Analysis Featuring Indago™ Debug Platform 6:00pm - 7:00pm Automotive Featuring ADAS and Safety Time Topic 10:00am - 12:00pm Verification Debug and Root-Cause Analysis Featuring Indago™ Debug Platform 12:00pm - 2:00pm HW-assisted Verification Featuring Protium™ and Palladium® Platforms 2:00pm - 4:00pm Formal Verification Featuring JasperGOLD® Apps 4:00pm - 6:00pm Simplify SoC Verification with VIP High-level Synthesis with Stratus™ HLS In-Depth Presentations and Demos (in Cadence tech suites) Regstration: http://www.cadence.com/dac2015/Pages/demosuitereg.aspx Monday Suite Session 11:00 AM Suite 1 JasperGold: Best-in-Class Formal by Far 02:00 PM Suite 1 Automating SoC Use-Case Verification with Perspec 03:00 PM Suite 1 SoC Performance Analysis with Interconnect Workbench Tuesday Suite Session 10:00 AM Suite 1 Functional Safety Verification for ISO 26262 12:00 PM Suite 10 Debug Automation for IP to SoC Designs 01:00 PM Suite 10 Indago Protocol Debug App Cuts SoC Verification Time 03:00 PM Suite 10 Hardware-Assisted Software/Hardware Development and Verification Wednesday Suite Session 01:00 PM Suite 1 Introducing Stratus High-Level Synthesis (HLS) Sessions at DAC June 8th Sunday Session Speaker(s), Panelist, Author Room 9:50am - 12:35pm System-to-Silicon Performance Modeling and Analysis (Workshop) Session 1: System-Level Design for Reliability Connecting temperature to power and performance analysis Steve Carlson 302 June 9th Tuesday Session Speaker(s), Panelist, Author Room 4:30pm - 6:00pm Embedded System Design - Models and Optimization Alicia Strang (Chair) 105 June 10th Wednesday Session Speaker(s), Panelist, Author Room 1:30pm - 3:00pm IP Strategies and Management Jason Sprott (Verilab), John Brennan 101 4:30pm - 6:00pm Verification from Transactions to Transistors Kei-Yong Khoo 310 June 11th Thursday Session Speaker(s), Panelist, Author Room 1:00pm - 1:30pm FPGAs and Increasing Security Requirements Chuck Alpert 303 1:30pm - 3:00pm From Algorithms to Bits: HLS and FPGAs Xingri Li Ryosuke Okamura Tsuyoshi Takabatake Qiang Zhu Alex Kondratyev 307![]()
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