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Embedded Vision Ripe for Growth, Rife with Challenges
SANTA CLARA, Calif.—Jeff Bier has some good news and less-good news when it comes to embedded vision applications. “The good news is there is an enormous and growing diversity of processor choices for...
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Multi-Language Verification Environment (#2) – Passing Items on TLM Ports,...
In the previous blog post , we created a simple multi-language verification environment, running UVCs implemented in SystemVerilog and in e . The architecture of the environment is as pictured here: We...
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How Ethernet Standards Are Born
I attend IEEE 802.3 Ethernet standards meetings and blog about them from time to time. ( For past blog posts, see the list at the bottom of this post ). The most recent 802.3 meeting was held in...
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DAC 2015: Tackling Tough Design Problems Head On
What are the biggest electronics systems design challenges of our time? Try mixed-signal implementation and verification. Try chip and system verification in general in an era when software is an...
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Five-Minute Tutorial: Innovus User Interface Tips
Hi Everyone, No doubt by now you have heard about the Innovus Implementation System , our next-generation physical implementation solution. It's always a bit scary to move to a new tool, but let me...
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Whiteboard Wednesdays—What's a Configurable Processor?
In this week's Whiteboard Wednesdays video, Chris Rowen discusses the basics of Tensilica configurable processors and what is involved in using them. (Please visit the site to view this video)
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Cadence Genus Synthesis Solution – the Next Generation of RTL Synthesis
Physical synthesis has been around in various forms for many years. The basic idea is to bring some awareness of physical layout into synthesis. This week (June 3, 2015) Cadence is rolling out the...
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DAC 2015 Cadence Theater – Learn from Customers and Partners
One reason for attending the upcoming Design Automation Conference ( DAC 2015 ) is to learn about challenges other engineers have faced, and hear about their solutions. And the best place to do that is...
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It’s Time to Modernize Debug Data and It’s Happening at DAC
“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog 1364-1995 and the open VCD syntax standard for debug data interoperability. Now the leading edge is over 1 billion...
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DAC 2015 – Join Us to Experience the Continuum of Verification and System...
The biggest yearly event in electronic design automation (EDA) is due to take over San Francisco next week, together, apparently, with the Apple developer community, to take over the Moscone Convention...
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The Birth of a New Era in Synthesis
When you have the best R&D team in the business and a vision to transform synthesis as we know it, well, great things can happen. And this week Cadence had a little birth announcement designed to...
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Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a...
In the previous blog post , we demonstrated connecting a checker implemented in SystemVerilog to a monitor implemented in e . In this post, we will show a fast way for adding a system-level data...
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Cadence JasperGold Brings Formal Verification into Mainstream IC Verification...
Formal verification is a complex technology that has traditionally required experts or specialized teams who stood apart from the IC design and verification flow. Taking a different approach, a new...
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Gary Smith at DAC 2015: How EDA Can Expand Into New Directions
First, the good news. The EDA industry will grow from $6.2 billion in 2015 to $9.0 billion in 2019, according to Gary Smith, chief analyst at Gary Smith EDA . Year-to-year growth rates will range from...
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Five-Minute Tutorial: The Innovus Standard Flow
Hi Everyone, Last week I highlighted a video featuring Innovus User Interface Tips . Now that you know how to get around, what next? Innovus has a new, more streamlined design flow. Most designs should...
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DAC 2015: Google Smart Contact Lens Project Stretches Limits of IC Design
There has been so much hype about the “Internet of Things” (IoT) that it is refreshing to hear about a cutting-edge development project that can bring concrete benefits to millions of people. That...
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DAC 2015: "Level of Compute in Vision Processing Extraordinary"-- Chris Rowen
SAN FRANCISCO--Cadence IP Group CTO Chris Rowen has been talking up vision processing for some time now, and he came to the 52nd Design Automation Conference to offer some additional perspective. In a...
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Multi-Language Verification Environment (#4)—Multi-Language Hierarchy
In the previous posts in this series on Multi-Language Verification Environment, we created a multi-language environment containing UVCs implemented in e and SystemVerilog. This environment is...
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DAC 2015: Can We Build a Virtual Silicon Valley?
SAN FRANCISCO—Can engineers use what Silicon Valley hath wrought to create a virtual Silicon Valley for the rest of the world? That was the intriguing question before panelists Wednesday, June 10 here...
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DAC 2015: Lip-Bu Tan, Cadence CEO, Sees Profound Changes in Semiconductors...
As a leading venture capitalist in the electronics technology, as well as CEO of Cadence, Lip-Bu Tan has unique insights into ongoing changes that will impact EDA providers and users. Tan shared some...
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