MaxLinear Addresses Capacity, Runtime, and Correlation Challenges with New Implementation Technology

MaxLinear, a developer of analog RF front-end semiconductors, previously used Cadence Encounter Digital Implementation System to tape out its chips. After getting an introduction to the new Cadence Innovus Implementation System, the company migrated its first 20nm chip to the new platform. In a talk at the Cadence Theater on June 8, 2015 (Session #10), at the Design Automation Conference in San Francisco, Prasanna Shah, sr. principal physical designer on the MaxLinear physical design team, shared his insights on the differences between the two tools. The design in question is a consumer electronics application chip, with a design block size of about 2.5M instances, clock frequency as high as 500MHz, and more than 10 clocks. Among the team’s challenges, according to Shah: placement congestion, tight area constraints, and timing closure within a specific window. Listen to Shah’s talk to learn about the differences in placement, clock tree synthesis (CTS), QoR, and runtime that he and his team experienced between Encounter Digital Implementation System and Innovus Implementation System . In the session, Shah also shares details about the improvements the team gained by migrating to the newer tool, from a reduction in implementation area to faster turnaround time to the close correlation with static timing analysis and with physical verification tools. Christine Young