It is always great to see when customers confirm what we in product management put forward as key elements for our product. As my team owns the product management for emulation, DAC 2015 in San Francisco was once again a great opportunity to check in with customers. And given that that imitation is the proverbial sincerest form of flattery, it was even nice to see the competition join the camp and putting more than their prime use model “Simulation Acceleration” forward by adding low-power caabilities. DAC 2015 confirmed that versatility of use models , a criterion we have been putting forward for years, more than ever is key for emulation and its return on investment (ROI). Not too long ago in 2014, we were discussing use models in a roundtable moderated by Ed Sperling and, as part of the Palladium XP II launch in 2013, my team and I wrote a whitepaper specifically on use models. And earlier this year, I sent a list of 23 different use models supported by the Palladium XP Series to Ed Sperling, which he covered in his article “ Emulation Uses Increase ”. The customer theatre at DAC 2015 was a great showcase of customer experiences with both Palladium and Protium platforms. Here are a couple of the highlights and you can even click through to watch the actual presentations: NVIDIA on Acceleration : Melanie Bianchi, Emulation Lead at NVIDIA talked about “ Delivering High Quality Denver IP Utilizing IP Acceleration ”. Melanie summarized nicely which methods work best for their testing and verification efforts, comparing the SoC level, unit level, and IP level. She described NVIDIA’s first steps to get something going fast and then honed in on how they enhanced the implementation. Her presentation gives great insights on how they were able to increase acceleration over simulation from 20X to 1000X (not bad in itself) by an additional factor of ten to reach 5000-9000X. AMD on Low-Power Verification and Optimization : Alex Starr, Virtualization Architect at AMD, delivered a great presentation called “ Experiences with Emulation-Based Power Intent Modeling ”. SemiWiki reviewed this presentation in more detail here . Alex reviewed a list of low-power challenges, from power management verification, dynamic power analysis, and application-level power monitoring to power intent verification. His slides illustrated nicely the complexity of different power domains in AMD's chips and how they decided which tests to run in emulation versu simulation. As we have been talking about in the System Development Suite since its inception in 2011, Alex made it clear without a doubt that both emulation and simulation have its place. He answered the self-imposed question “Was it worth it?” with a resounding YES! With little overhead, AMD was able to drastically reduce long simulation runtimes, run closer to real life workloads, and test more complex SoC power interactions not possible in simulation. ARM on Emulation – Virtual Platform Hybrids: Rob Kaye, Technical Specialist at ARM focusing on system modelling, updated the DAC audience about “Hybrid Virtual Prototyping Solutions for ARM-Based SoCs”. We publicly presented on this at CDNLive here . ARM themselves had achieved 50X faster OS boot-up on Mali GPU development using Palladium XP running in conjunction with their fast models. Netspeed on Coherency Verification: JJ Tuan, Chief Verification Architect, presented on “ Using Palladium Platform to Exhaustively Verify a Configurable Coherent NoC IP ”. JJ gave an overview on how staggeringly massive the verification space for coherency really is and concluded that coherency verification really requires emulation, for which they use the Palladium platform. They ran the Palladium platform at an average speed of 5.4MHz and what previously took them weeks was completed in minutes. Cadence/ARM on Verification for ARMv8-based SoCs: I ended up presenting on “ Verification Solutions for ARMv7/v8-Based Systems on Chip ”, which includes Palladium Hybrid for early OS and software bring-up, Perspec System Verifier for software-driven use case verification for ARMv8-based designs, Palladium Dynamic Power Analysis for profiling real traffic, Indago Debug Analyzer synchronized embedded software debug on ARM RTL CPU, System Integration Automation packaged ARMv8 IP and VIP for fast SoC integration, Interconnect Workbench for SoC verification and performance analysis, and our VIP Portfolio with ARM AMBA ACE support in Incisive, JasperGold, and Palladium technologies. JP Media/SRISA on Emulation and FPGA-Based Prototyping Adjacencies : John Blyler presented on “ Case Studies for Successful FPGA-Based Prototyping ”. For us at Cadence, Palladium emulation and Protium FPGA-Based Prototyping go hand in hand. John described some of the key needs for prototyping that he derived from his surveys, and then showed a success story presented by SRISA at CDNLive EMEA, illustrating how they were able to use Palladium and Protium solutions in conjunction and were able to achieve 10M instructions basically out of the box, an almost 15X improvement over the Palladium platform using the same front end but trading speed for less debug. Bottom line, DAC was a great confirmation that versatility of use models is key for emulation. Our customers are not only using the Palladium platform for tens of projects in parallel, but also for different use models. And there is no shortage of new use models still to come, as, for example, George Zafiropoulos from National Instruments presented on post-silicon testing and its connections to pre-silicon verification . Use model versatility as found in the Palladium XP platform makes the best use of emulation as a very valuable resource. Frank Schirrmeister![]()
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