Earlier this week, Cadence announced the Joules RTL Power Solution, which provides time-based RTL power analysis with system-level runtimes and capacity, along with high-quality estimates of gates and wires. I chatted with Jay Roy, software engineering group director for Cadence’s synthesis R&D team, to get the scoop on how the Joules RTL Power Solution can improve RTL power analysis. First off, tell me about the team behind the Joules RTL Power Solution. My team includes engineers in the US and in India (Noida and Bangalore), with RTL power analysis experts as well as folks who work on our Genus Synthesis Solution. While the Joules solution has many standard utilities, some customers also request certain enhancements. So our engineers are working very closely with customers to make sure their needs are met. How are engineers currently estimating RTL power? Why are these techniques insufficient? Power is a confluence of design implementation (synthesis, P&R) and verification (stimuli through the design). Existing RTL tools lack the synthesis and P&R technology pieces. As a result, their power estimation at RTL is inaccurate and unpredictable. Furthermore, these tools can process only one stimulus at a time, making the process of power analysis over many scenarios very slow. So, customers end up doing power analysis after synthesis and P&R using tools like our Voltus IC Power Integrity Solution. The estimated power after synthesis/P&R is accurate, but the data comes very late. The Joules RTL Power Solution seems to interact with multiple stages of the design flow. Why is that, and how does benefit the user? In a typical design, there’s verification, implementation, and signoff. Verification engineers generate a lot of activity files and want to know if they can view power profiles for these activity files. Implementation engineers have plenty of RTL activity files and want to use these files on their netlist for power reduction. As for signoff, by the time these engineers get the designs, the designs are very heavy and gate simulations are too slow. They want to extract peak power windows from the RTL activity for signoff analysis. The Joules solution connects these three disciplines of chip design. As a block-level power calculator and SoC-level power aggregator, the Joules solution works at RTL and at gates to deliver predicable accuracy and performance, advanced stimulus handling, and data mining and debug. Because the Joules solution has an implementation engine in it, it translates RTL names into gate-level names so that implementation engineers can use RTL stimulus on their netlist to profile power. With the tool’s peak frame identification function, signoff engineers can use their existing system-level tests for power signoff. Tell me about the multi-frame architecture and how it helps users identify peak power situations. The multi-frame architecture gives users the flexibility to select the number and size of power frames, along with the ability to scan large simulation windows and zoom in and out as needed. For example, say an SoC has audio, video, and security blocks along with IP. The engineers might have tests on the different blocks to show peak power areas. With the Joules RTL Power Solution, the engineer can break up each stimulus into frames of their choice and compute the power for each frame to generate an overall power profile. If in a particular frame the power peaked, the user can zoom into that frame to get more details. This capability gives engineers the flexibility to scan things quickly to get a full picture of power, and the resulting data can be sent to the Voltus solution for power signoff. Other tools can only perform one stimulus at a time. How did your team’s collaboration with other engineering divisions within Cadence impact the Joules RTL Power Solution? The Joules team collaborated with several Cadence divisions/products, which resulted in various features and capabilities. These include: Genus Synthesis Solution – The Joules solution uses Cadence’s production synthesis engine and timer in a fast mode for design implementation. Innovus Implementation System – The Joules solution estimates clock-tree and P&R data buffers by modeling the way the Innovus tool creates clock-tree buffers and insert placement buffers. Voltus IC Power Integrity Solution – We collaborated with this team to tune the Joules power engine and make it consistent with that of the Voltus solution, which is Cadence’s power signoff engine. Palladium XP verification computing platform – We collaborated here to extract activity (stimuli) directly from the Palladium platform’s PHY database. Tell me more about the capabilities that are possible since the Joules solution is integrated with Palladium technology. We've integrated the Joules solution with Palladium Dynamic Power Analysis to provide early system-level peak power identification. This integration brings the benefits of deep Palladium cycles and Joules accuracy, shortening the time needed for power analysis. Users can invoke the Joules RTL Power Solution directly from the Palladium Dynamic Power Analysis solution and can report time-based power waveforms natively within the Palladium GUI. As we move into even smaller process nodes and SoCs continue to become more complex, what is next on the horizon for RTL power analysis? The good thing about RTL is, it’s fairly independent of the shift in the technologies. The pieces that connect RTL to the technologies are the implementation tools, so the same RTL can be implemented at 10nm or 65nm. The key thing is for the power analysis tool to have one leg in the implementation domain, and the Joules solution has this. The second piece is the stimulus side. Going forward, as technology evolves even more, other tools are going to be more hard pressed on the activity front, while Joules technology is in a good position. As process nodes shrink and devices become more dense, simulation and emulation will need to run faster. So the combination of Palladium and Joules technologies is good news for our customers. Christine Young![]()
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