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What's Good About Allegro PCB Editor Disable of Open Space Routing? 16.6 Has It!
By default, the 16.6 Allegro PCB Editor ‘Add Connect’ command generates routes when a pick is made on database elements like pins or vias, but also when a pick is made in open or black space. Designers...
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ARM's Hobson Bullman Talks Tools for Addressing Chip Design Complexity
How are you dealing with increasing chip design complexity? For ARM’s Hobson Bullman, it’s all about the tools. Bullman, general manager of the company’s Development Solutions Group, presented a talk,...
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Whiteboard Wednesdays - LPDDR4 for Automotive Memory
In this week's Whiteboard Wednesdays video, Kishore Kasamsetty discusses why LPDDR4 is the right choice for automotive memory designs. (Please visit the site to view this video)
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Double-Take: Improving Validation Test Suite with System-Level,...
Application Spotlight When Freescale wanted to measure the coverage of their validation test suite for their automotive products, they determined that that the memory map coverage approach wasn’t...
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ams Shortens Design Cycle via Electrically Aware Design Flow
It's never fun, finding problems in your design—especially when you find them late in your design cycle. That was the frustration that ams faced, until the company integrated an electrically aware...
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Whiteboard Wednesdays—More on Camera Subsystems
In this week's Whiteboard Wednesdays video, the second in a three-part series, Pulin Desai goes into more detail on the function of each individual block within a camera subsystem. (Please visit the...
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What's Good About Allegro PCB Editor DRC by Window? It’s in the 16.6 Release!
The 16.6 Allegro PCB Editor ‘DRC by Window’ command is an alternative to running DRC update at the full design level. As the name suggests, the command is limited to checking the elements within the...
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Manage Your Shapes with Ease in the Latest 16.6 ISR of Cadence APD and SiP...
Shapes. Whether it’s a split plane, a power ring or flag under your die, or a cavity outline, they abound in any IC package substrate. Some are filled, others cross-hatched or even degassed. Whatever...
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Q&A: Engineering Director Jay Roy Shares Insights on New RTL Power Analysis...
Earlier this week, Cadence announced the Joules RTL Power Solution, which provides time-based RTL power analysis with system-level runtimes and capacity, along with high-quality estimates of gates and...
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Q&A with Anne Hughes—DDR IP Engineering
Memory is a ubiquitous component in today’s electronic devices, and advancements in the technology are resulting in higher performing, lower power memory products. Anne Hughes is a design engineering...
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Cadence ONFI 4.0 Flash Memory IP Increases Data Access to 800Mtps and Reduces...
Announcing Availability of ONFI 4.0 IP Flash memory applications have expanded from USB Flash Drive “sticks” to solid state drives (SSD) and beyond, as designers demand increased non-volatile storage...
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DAC 2015: How Best to Manage Third-Party IP Integration
SAN FRANCISCO—Third-party IP integration is crucial not only to managing system-on-chip (SoC) design complexity but getting to market in a reasonable amount of time. But this is often easier said than...
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Electrical Validation of DDR4 Interfaces
Developing SoCs with high-speed memory interfaces, such as DDR4, presents substantial challenges throughout the design process. Today’s high-performance semiconductor processes enable high-speed...
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Whiteboard Wednesdays—Managed NAND Flash Devices
In this week's Whiteboard Wednesdays video, Lou Ternullo provides a detailed overview of managed NAND flash devices and system design considerations. (Please visit the site to view this video)
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Socionext Explains Why High-Level Synthesis Is a Winning Technology for IP...
Have you been weighing the pros and cons of replacing a hand-coded RTL methodology with high-level synthesis (HLS)? For Socionext, using HLS certainly yielded benefits in performance, power, and area...
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What's Good About Allegro PCB Editor NC Route? 16.6 has Several New...
There are a few NC Route enhancements in the 16.6 Allegro PCB Editor release. Read on for more details … Separate plated vs. non-plated files An option has been added to the NC Route user interface to...
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Whiteboard Wednesdays--Evolution of Automotive Electronics
In this week's Whiteboard Wednesdays, Charles Qi talks about the evolution of electronics in the automotive industry and the challenges and opportunities faced by suppliers today. (Please visit the...
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Cadence IP for USB Works over Type-C (Proof Inside)
There is no other specification in the history of USB that caused so much discussion and interest as the USB Type-C. The new type of connector, designed to be a jack of all trades, eliminates all flaws...
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Q&A: Anne Hughes on Memory IP Advancements and Women in Tech
Memory is a ubiquitous component in today’s electronic devices, and advancements in the technology are resulting in higher performing, lower power memory products. Anne Hughes is a design engineering...
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Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger
Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement Optimization . The next step in the flow would be inserting clock trees. Now that we can take advantage of the...
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