Developing SoCs with high-speed memory interfaces, such as DDR4, presents substantial challenges throughout the design process. Today’s high-performance semiconductor processes enable high-speed design, and require expertise in signal integrity design, timing closure, and system bring-up. One of the biggest challenges is co-designing the memory interface, the chip package, and the PCB to preserve the high-speed signal integrity. Cadence collaborated with Tektronix to develop electrical design and validation solutions for DDR4 and LPDDR4 operating at the latest 3200Mbps speeds. Tektronix provides analysis tools and software to analyze the collected data. Cadence Sigrity tools are linked with the Tektronix solution, enabling pre-silicon simulation results to be analyzed as part of the process of ensuring signal integrity from chip to package to board. Cadence used this solution to design and validate its DDR4 and LPDDR4 interface IP as we collaborated with other industry leaders such as HiSilicon, which you can read about here . Brad Griffin, product marketing director for Cadence, and Prashanth Thota, senior marketing manager at Tektronix, delivered a webinar describing how to design and validate a DDR4 interface from chip to package to system level. Using the Cadence DDR4 IP Reference Design as a case study, the webinar explains how to use the Cadence Sigrity solution to design the chip, package, and board, and measure the device with Tektronix test equipment to measure compliance. Watch the webinar here . Evan Green![]()
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