Have you been weighing the pros and cons of replacing a hand-coded RTL methodology with high-level synthesis (HLS)? For Socionext, using HLS certainly yielded benefits in performance, power, and area for its advanced IP and SoC designs. A developer of SoCs and software for video/imaging and networking applications with headquarters in Yokohama, Japan, Socionext was one of about 50 Cadence customers who shared their experiences, lessons learned, and best practices at the Cadence Theater at this year’s Design Automation Conference (DAC) in San Francisco. Most of these presentations are now available online for viewing. In his talk, “High-Level Synthesis: a Winning Technology,” Masato Tatsuoka from Socionext’s front-end design department in its SoC Design Division walked through the company’s journey. Meeting Quality, Productivity Needs with HLS Design Methodology As Tatsuoka explained, Socionext had two key goals for enhancing the design process for its solutions, essentially custom ASICs: Establish an HLS design flow to meet the market’s need for quality, productivity, and fast time to market Achieve higher quality of results for every IP designed using HLS vs. hand-coded RTL. To this end, every large design using HLS should achieve first-silicon success with at least twice the productivity that a traditional RTL design flow can provide. Three Key Technologies to Meet the Goals As systems continue to grow larger and more complex, Socionext recognized that it would be difficult to achieve its goals using traditional RTL. That’s why the company turned to an HLS flow. Working with Cadence, Socionext: Applied interface-based design, separating the interface from the behavior using a transaction-level modeling (TLM) approach. Tatsuoka explained that by optimizing not only functions but also the interface and control, you can avoid mismatched protocols and easily optimize communication between blocks. Protocol mismatches often occur when HLS blocks connect to hand-coded RTL. Sometimes, problems aren’t detected until verification. Performed early micro-architectural exploration to find the best hardware implementation, one that balances performance, power, and area. This is almost impossible to do with a traditional RTL design flow, said Tatsuoka, but it’s relatively easy using HLS. Reduced back-end risk by introducing a physically aware HLS design flow. The engineers also introduced congestion detection and congestion improvement steps prior to place and route, and integrated an existing physically aware logic synthesis tool in the mix to detect congestion and find its root cause in SystemC. “These three key technologies helped us achieve great success,” noted Tatsuoka. Case Studies Spotlight Performance and Power Benefits To highlight their success, Tatsuoka shared two case studies. In one case, Socionext applied HLS to a DMAC IP design with complex ARM® AMBA® 3 AXI interfaces. The resulting design had 35% higher performance, 35% less area, a 51% reduction in power, and 2/5 the lines of code, compared to an existing hand-coded RTL IP design. The second example was a 4K/p60 HEVC video encoder, where 90% of the design used HLS. The encoder, which achieved first-silicon success, has only 1/20 th the volume and 1/50 th the power of a multiprocessor system, with 1000X the performance. “HLS technology is the key to winning in future IP and SoCs designs that require high quality, high productivity, and rapid time to market,” concluded Tatsuoka. Hear Tatsuoka’s talk and view his slides here from Session 31 (5:00pm on Tuesday, June 9, 2015). Christine Young![]()
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