While the Internet of Things (IoT), mobile, and automotive markets are fueling growth in the semiconductor industry, there are still formidable challenges for engineers to address. That’s why it will take close collaboration across the design ecosystem to achieve continued progress and innovation. That was the sentiment at TSMC’s Open Innovation Platform® (OIP) Ecosystem Forum on Thursday, Sept. 17, 2015, at the Santa Clara Convention Center. TSMC North America President Rick Cassidy opened the day of technical sessions with a welcome address t hat highlighted the key growth drivers and some of the strengths of TSMC, from its ultra-low power platform to its advanced packaging technology, R&D spend (a 19% increase this year over last), and its capacity (delivering more than 1.6 million 8-inch-equivalent wafers each month). “We need to make sure you can leverage that capacity when you need it,” Cassidy noted. “Nobody does yield better than TSMC.” Committed to Technology Leadership A full audience in the convention center ballroom then heard keynotes on themes of technology leadership, collaboration, and innovation from two of TSMC’s top technical experts. First up, Dr. Jack Sun, VP of R&D and CTO, spoke on “Technology Leadership for Collaborative Innovation.” Sun highlighted several areas that demonstrate TSMC’s commitment to technology leadership. For example, in the area of advanced logic technology for mobile and high-performance computing, TSMC has: Delivered more than two dozen tapeouts and high-volume production at 16FF+ Produced a functional 7nm SRAM test chip Demonstrated excellent chip-level power, performance, and area (PPA) scaling at 10nm, its third-generation FinFET process Continued to push material and transistor structures, conducting exploratory research into sub-10nm processes Made good progress on extreme ultraviolet (EUV) lithography and other advanced patterning technologies to further drive scaling The pure-play foundry has been able to achieve steep yield ramping through continued yield learning. With each process shrink comes improvements in speed and power. By the time the 7nm process is in production in early 2017, customers can expect 10-15% better speed, 25-30% power reduction, and about 1.6X density improvement, Sun noted. Staying Ahead of Moore’s Law “We continue to (move) ahead in Moore’s Law and logic and we continue to expand our specialty technology portfolio, which covers many types of sensors, embedded flash, embedded memories….Most importantly, we have our ultra-low power platform to support Internet of Things applications,” said Sun. “Nobody else in the world has this type of depth and breadth of offering.” Dr. Jack Sun; photo courtesy of TSMC How has TSMC achieved its power advances? Sun described a mix of techniques, from simply reducing supply voltage to extending the high-Vt device for leakage control, developing a low-leakage SRAM bit cell, and making Ideff improvements for better speed. In the automotive industry, explained Sun, TSMC leads with more than 40 customers, more than 500 tapeouts, and more than 1 million 12-inch-equivalent wafers shipped. The foundry offers the most complete portfolio for automotive technology, including embedded flash, CMOS logic, and CIS. Speaking about wafer-level system integration technology, Sun discussed two of TSMC’s offerings here: Chip-on-Wafer-on-Substrate ( CoWoS ), which uses through-silicon via (TSV) technology to integrate multiple chips on a single device, and Integrated Fan Out (InFO) packaging technology, which supports multi-chip integration with the smallest form factor. Using CoWoS and InFO together can result in high bandwidth and low power, noted Sun. “We will continue to enhance and enlarge our specialty technology platforms,” said Sun. “We will provide the most advanced, most compact, and energy-efficient wafer-level packaging to provide the true value of system-level integration.” Why More Features Are Needed from EDA Tools Next, Dr. Cliff Hou, VP of R&D of Design Technology Platform at TSMC, discussed “Collaborative Ecosystem Innovation for New Opportunities.” While TSMC will continue to push the technology envelope to deliver the best PPA, the company values the role of its design ecosystem to address increased process complexity, Hou said. Over the last 10 years, for example, the increase in design rules has necessitated more EDA features to keep runtime in check. As a result, TSMC engages early with its EDA partners and its IP partners, to help deliver tools one month in advance and IP six months in advance of process availability. During his keynote, Hou introduced two TSMC customers, who spoke about their experiences with collaboration. Frank Ostojic, Sr. VP and general manager of Avago, talked about trust and risk. “Being ahead depends on how much trust you can put on your partners and your engineering team and on how much risk you are willing to take,” Ostojic said. How do you trust someone? “You ask them for a status and for 10 bullets and if all the 10 bullets are good news, you don’t trust them,” Ostojic said, drawing laughter from the crowd. On a serious note, he noted that trust comes when a partner, as in the case with TSMC, provides a realistic picture of the risks that need to be managed, along with the good news. Victor Peng, executive VP and general manager of products at Xilinx, talked about the string of successes needed to establish a leadership position and the importance of partnerships in this process. “We have a flow, standard-cell place and route, and we do a lot of custom design. There’s more complexity in design rules and in proximity effects. If it weren’t for the EDA suppliers working in concert with the foundries and working in concert with the IP providers, we couldn’t get these products out,” Peng said. Dr. Cliff Hou; photo courtesy of TSMC Wrapping up the keynote session, Hou summarized, “We truly believe that, with our collaborative innovation, we can have a win-win-win for all of those opportunities ahead of us.” Christine Young![]()
![]()
↧