7nm is already passé it seems! Today Cadence and imec announced the tapeout of the first 5nm test chip. Actually it is two chips. These use a combination of extreme ultra-violet (EUV) along with traditional 193nm immersion lithography (193i) with self-aligned quadruple patterning (SAQP). Taping out the design, required the two companies to optimize design rules and libraries and the physical design system itself. The physical design was done using a special version of the Cadence Innovus Implementation System. The basis of the design was a processor. You can read the press release , which contains the usual press release level of detail. This afternoon, I talked to Vassilios Garousis, Cadence Distinguished Engineer, to get some more color and even a screen-shot of how the cut mask works. It is not a true test chip, in the sense that all layers were created. The focus has been on the limits of different sorts of lithography for metal2, via and metal3. There are no devices (transistors) in the tapeout. However, full reticles were created and the impact of lithography on timing and power was calculated. The patterning and measurements will help imec, ASML (manufacturer of the EUV equipment) and foundries to understand the limits and see issues based on the tighter pitch. Both test chips are a great milestone for the industry and also for Cadence to make sure that the toolchain can address these advanced nodes. A little detail on SAQP. The most common form of double patterning is called LELE, or litho-etch-litho-etch. The advantage is that it is straightforward but the disadvantage is that it is not self-aligned and so gives up some pitch. For example, the limit to single patterning with 193i is 80nm. With LELE you can get to 50nm, not the 40nm you might expect. The next step is self-aligned double patterning, or SADP. For this a sacrificial mandrel is laid down with single patterning and then a spacer is formed on the side of the mandrel. The mandrel is removed, leaving patterns at the double patterned pitch but self-aligned and so the pitch can be tighter. SAQP takes this to the next stage. Once the mandrel is removed, the spacers are doubled by forming new spacers on either side of the first-generation spacers, which are then removed. This leaves a grating of metal, which is then cut to separate the metal into its individual elements. One change at 5nm is that the cut “mask” cannot be manufactured as a single mask (using 193i); it too needs to be made with multiple patterning and so multiple masks. In turn, this means that the Innovus physical design system needs to be aware of the cuts since they must be colorized. In a sense, it is the next step after first requiring the routes to be colored, then also the vias, and now the cut masks, too. Of course the big issue is not the coloring itself, but the fact that not every combination of routes is manufacturable, even if the routes and the vias themselves are colorable. The entire design was taped out, including both the processor and SRAM with full device models, parasitics and timing closure. However, only M2-via-M3 were actually taken all the way to mask. Multiple different options for the metallization were created. All SAQP. This requires four masks to create the M2 lines and then a double-patterned cut mask. The via requires three masks and is two-colored. M3 is the same as M2. Mixed SAQP and EUV. This makes the M2 and M3 lines with SAQP but then uses a single EUV cut mask for each. The vias are also a single EUV mask. The M2 and M3 masks are the same as in the first option. All EUV. In this case the metal layers are printed and single-patterned with no requirement to cut (thus, obviously, no cut masks). Contacts were a single EUV mask, which was also the same mask for the second option. Further options were created by scaling the metal pitch down from the nominal 32nm to manufacture to 24nm, which is the limit for SAQP. There are not only implications for manufacturing tolerances and manufacturing costs. If all cells are done with a cut mask then there is a little higher capacitance and thus higher power and lower performance. This is a big deal since the major drivers for the most aggressive processes are the application/modem processors for smartphones, which require a big increase in performance and a reduction in power for each generation, or else there is little point in moving (since there is no cost reduction). On the imec side the work was done by An Steegen’s team. She is the SVP of process technology. As it happens, imec flew me to Belgium for their symposium in the summer and I spent an hour with her quizzing her on which of the esoteric technologies being talked about she thought would be successful, and thus what our process roadmap was going to look like for the next decade. Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. That's a pretty good summary. It requires changes to libraries, changes to the physical design software and, obviously, a lot of work on process, especially lithography. Behind it all remain questions about EUV for use in high-volume manufacturing, but that’s for another time. Now a trick question. On a 5nm process, what is 5nm? Well, there is nothing really measuring 5nm physically. Just as at 10nm, different foundries will make different decisions, just as Intel 14nm is not a lot looser than TSMC 10nm. So 5nm might cover a metal pitch anywhere from around 36nm down to 24nm.![]()
![]()
↧