In my first real blog here, about the Cadence/imec 5nm announcement, I asked what was 5nm on a 5nm process. The answer is nothing. Creating the lithography for 5nm is a major milestone but process naming has become very misleading. It reminds me of that old Bonzo Dog song Shirt where one little part of the lyrics is: Good morning. Could I have this shirt cleaned "express," please? Yes, that'll be three weeks, dearie. Three weeks? But the sign outside says 59-minute cleaners! Yes, that's just the name of the shop, luv. We take three weeks to do a shirt. In the same way “5nm is just the name of the process. It takes 30nm to do the metal.” If you think about it, it would be really difficult to actually make 5nm metal. That is 50Å but the atomic diameter of copper is 12.8Å so the metal would be just four atoms wide. Even at 30nm that is only 24 atomic diameters across. Back in the stone age of semiconductor, the process name such as 1um (what we now would call 1000nm) really was the gate length. There was sometimes a little specmanship around whether it was the drawn gate-length, the effective gate-length, or the gate-length after mask-skew, but these were all pretty close anyway. The metallization also tracked pretty closely since the main limitation was lithography, which was the same on all layers. But today that is no longer the case. As An Steegen of imec said, “Ah…what’s in a name? Actually, not that much any more.” It’s just the name of the store. One important number is 80nm. We have been limited to 193nm light for lithography for years. With immersion lithography, off-axis illumination and aggressive OPC it is possible to use single patterning down to a pitch of 80nm. By some sort of unspoken agreement, this corresponds to a process name of 22nm. This means that 22nm processes are single patterned, while 20nm and below require double patterning. With litho-etch-litho-etch we might theoretically be able to get down to 40nm but due to misalignment between the two double-patterning reticles, we lose 10nm and end up with a minimum half-pitch of 50nm. With SAQP, as on the 5nm test chip, the theoretical limit would be 1/4 of the 80nm we can achieve with single patterning, but we need to add some slack to make up for various imperfect processing. In fact one of the points of the 5nm test chip is to find out what that limit is, with metals scaled from 36nm down to 24nm. The 5nm testchip also has a variation with EUV masks. EUV light is 13.5nm so the wavelength should not be the limiting factor to how low we can go. One of the other issues in these very advanced processes is what restrictions are put on the designer. With SAQP and a cut mask (actually multiple cut masks) the patterns can only be one dimensional. With EUV, in principle they do not need this restriction, but there has been so little experience with EUV that the yield impact of putting "L" and "T" shaped patterns on the mask are not fully understood. In practice, they may need to be one dimensional too, and they certainly need to be if foundries decide to add EUV as an option, using SAQP as a fallback. The process roadmap for everyone goes 10nm, 7nm, 5nm. Not everyone is using the same pitches at 10nm and nobody is saying anything public about 7nm. One of the reasons for building the 5nm Cadence/imec testchip is to see what are the practical tradeoffs between smaller pitches, yield, and timing at the 5nm node. But all processes with the same name are not the same. Some 59-minute cleaners only take two weeks. So when the question is “what does 5nm mean?” the answer is, or will be, “it depends.” But with this test chip, we will have a much better idea of what is possible.![]()
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