Let's pull a paragraph out of the joint Cadence/GF press release from earlier today. Cadence collaborated with GLOBALFOUNDRIES on the development of the Process Design Kit (PDK) for the 22FDX platform. The Cadence digital implementation tools support the capability of forward and reverse body bias (FBB/RBB) to optimize the performance/power tradeoffs, tap insertion and body bias network connectivity according to high voltage rules. What does all that mean? What is 22FDX? What is body bias? To understand we need to start by going back to planar transistors, the type that everyone used down to 20nm (except for Intel, who switched earlier). By 28/20nm planar processes were running into problems. The channel area underneath the gate was getting very short and the gate was no longer powerful enough to control it properly. It could control the top part of the channel but the further from the gate, the less the control. In particular, when the gate was off there were paths between source and drain that remained on (known as "punch through") and so there was very high leakage. The diagram shows the leakage paths. For Moore's Law to continue, it was clear that a new transistor architecture would be required. The basic constraint was that all of the channel needed to be close to the gate so that it could be controlled properly. One way to do this was to make the channel into a thin vertical fin (like a shark's fin, that is where the name comes from) and wrap the gate around it, which gives you FinFET. Since the fin is thin, it is never far from the gate and control is good and leakage is low. There are some other issues such as self-heating and the number of masks required, but for the leading-edge designs FinFET is the transistor architecture of choice. The alternative is to go horizontal. If a thin channel is put on top of an insulator, and the gate is built on top of that, then there is once again good control and low leakage. There are simply no paths through the channel that are far from the gate and so poorly controlled because the insulator...well, insulates. Current cannot flow there. The transistor is not quite as good as FinFET since it only controls one side of the channel, but it is a lot easier to manufacture. That is thick-box FD-SOI (box just stands for buried oxide, the insulator underneath the channel). If, however, the box is very thin then, in effect, the substrate itself becomes a sort of second back gate and can further be used to control the channel, not strongly enough to turn it on and off, but to affect its performance. This diagram shows how forward body bias (FBB) works. FBB of up to about 1.8V can be applied. When higher performance is required the FBB is applied. The transistors are faster at a cost of slightly higher leakage. When the design is in a standby mode of some sort, then the FBB can be removed to reduce the leakage again. Alternatively, the power supply voltage can be reduced, which would slow the transistor down too much to meet timing, and then FBB can be used to speed it up again. But the voltage is still down, reducing leakage and, of course, dramatically reducing dynamic power (voltage is squared in the power equation). In an analogous way, reverse body bias (RBB) can be used to reduce leakage at the cost of lower performance. The FBB/RBB can be varied (although not extremely fast) under software control to adapt the power/performance to the needs of the operating mode of the chip. Thin box FD-SOI was developed originally by ST Microelectronics at 28nm. A couple of years ago GLOBALFOUNDRIES licensed it (and then so did Samsung). But for a long time nothing was announced. It turned out that GF had been investigating its relevance to their customer base. Their customers wanted more performance so they developed a 22nm version called 22FDX. Actually there are four different processes with slightly different characteristics (ultra-low power, ultra-low leakage, high performance, RF and analog). Using FBB the operating voltage can be as low as 0.4V, which Gary Patton, the CFO of GLOBALFOUNDRIES, told me he believes is the lowest operating voltage of any process in production or development. The press release today announced that Cadence's digital and signoff tools have been qualified for the GLOBALFOUNDRIES 22FDX platform reference flow. An ARM Cortex-A17 processor was used as the vehicle. The flow includes support for FBB/RBB and all the other features of the process such as double-patterned metal1, implant-aware and continuous diffusion-aware placement, and design-for-manufacturing (DFM). Cadence's Voltus IC Power Integrity Solution and Physical Verification System (PVS) is in active qualification. The rest of the implementation flow (the Genus and Innovus tools) are already qualified, as are the other signoff tools (Quantus QRC and Tempus solutions). There will be a presentation at ARM TechCon titled The Implementation of ARM Cortex-A17 Quad-Core in GLOBALFOUNDRIES 22FDX Technology Using Cadence Innovus Implementation System . The session is scheduled for 2:30pm on Thursday in the Mission City Ballroom M3 at the Santa Clara Convention Center. Cadence is involved with a dozen presentations during the conference. Of course, Cadence will also have a booth in the exhibition with regular presentations on all things ARM. Plus, the doctor is in: the Cadence Expert Bar will be in the booth with engineers ready to talk about software debug, AMBA, ARM IP and more. Full details on Cadence's involvement in ARM TechCon are on a special webpage .![]()
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