Documentation plays a significant role in helping to understand the software. Cadence is putting in lots of effort in developing different forms of documentation, from product manuals to videos, application notes, tutorials, Rapid Adoption Kits (RAKs), and point solutions. We are kicking off a new series to highlight interesting and useful content which gets added to Cadence Online Support . Types of documents on Cadence Online Support Rapid Adoption Kits (RAKs) – RAKs help you learn the tool's features and flow quickly. RAKs usually consist of a working database and detailed manual to proceed and may contain a video. Application Notes Videos Troubleshooting Information – Point articles. Product Manuals Access these documents through the Resources menu. RAKs SiP Allegro Design Entry HDL Exporting a Die Abstract from Virtuoso IC 6.1.7 to SiP and OrbitIO This RAK provides example Virtuoso® databases and instructions for creating a die abstract from Virtuoso IC 6.1.7 and later versions for Cadence® SiP and OrbitIO. Controlling Default Stacking Behavior of Symbol Properties This document describes the methodology to control the spacing between stacked symbol properties in Allegro® Part Developer. Videos Allegro PCB Editor Allegro Productivity Toolbox - ZDRC ( Z-axis DRC Clearance Checking ) A brief overview of the Allegro PCB Productivity Toolbox option and the ZDRC Clearance Checker utility, followed by a brief demo of ZDRC. Generating Blind and Buried Vias Describes how to generate blind and buried vias in Allegro PCB Editor. Application Notes Sigrity SiP Allegro PCB Editor Allegro Design Workbench PowerDC Shield Can Thermal Simulation The application note describes the steps necessary to create a thermal model of a shield can in Sigrity PowerDC. Early Die bump planning using SiP Layout with EDIS This application note describes the process for early IC bump planning and data exchange based on DEF and die abstract. SKILL Code Routine Implementationn This application note outlines the process to execute a SKILL Code Routine on an Allegro PCB Editor Board File. ADW - Using bulk edit to make large part classification changes This document shows a simple procedure to move large parts to the new classification in the Database Editor. Sigrity OptimizePI: Post Simulation What-if Analysis Tips This document shows how to add more model types to choose from without disturbing the pre-computed data file. RLC Parasitic During Interactive Routing in SiP Layout This application note explains how the RLC feature can be used during the interactive routing process to specify limits or constraints. Usage of Different Arguments When Running NETREV in Batch Mode The document describes the different arguments used when running Netrev in batch mode. ADW Flow Manager Default Web Browser This document explains how ADW Flow Managers can configure and change the default web browser for Flow Manager launch commands. Creating Manual Excitations in Allegro Sigrity This application note explains how to create custom excitations in the Allegro Sigrity tool. Importing Microsoft© Excel XML spreadsheet into SiP Layout This application note describes the generic process for importing the Excel spreadsheet information into SiP Layout. Troubleshooting Allegro PCB Editor Display Issues This document helps users debug scenarios where Allegro PCB Editor stops responding or the display freezes. Self-learning videos to learn more on the tools can be seen from Training Bytes . New videos have been published for: · Allegro Design Entry HDL · Allegro PCB Editor · Sigrity Power and Signal Integrity Thanks for reading. You may visit Cadence Online Support to read more. Leave a comment if there are any items you found particularly useful that you'd like to share with others. Jasmine![]()
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