It’s an ongoing challenge faced by universities across the globe: How to teach advanced-node design to the next generation of SoC engineers when budgets are tight and access to the latest tools and technologies is limited? For Dr. Matthew Swabey, deputy director of instructional laboratories at Purdue University’s School of Electrical and Computer Engineering, his focus is on giving students realistic experiences that would be useful in research and in industry. Partnerships with companies are critical, as is access to educational licenses for software, he noted during his talk in early April at CDNLive Silicon Valley. Swabey’s session was part of the first Academic Track, sponsored by the Cadence Academic Network, at the Silicon Valley conference. Swabey began his talk by outlining some points of concern—namely that the semiconductor market has added $90 billion in the last 10 years but there hasn’t been a corresponding increase in academic ASIC activity. In fact, many universities haven’t moved to 90nm and smaller technologies and there’s also a decline in research groups and universities prototyping designs, he said. Yet, the common paths for ASIC undergrads after they’ve completed their studies is to either go to graduate school (and pursue VSLI and EDA research or system/module research) or transition into industry via internships and then on-the-job training, he said. So, students need the foundation that practical experience provides. “From my perspective as an educator, I don’t like the way things are shaping (up),” Swabey said. Barriers to Maintaining an ASIC Flow in the Classroom From his vantage point atop the “ivory tower,” Swabey sees the following requirements and steps for universities to set up and maintain an ASIC flow: Cost-effective access to a manufacturing fab IP Establishing a flow EDA tools, along with training Designing the chip Updates to all of the above Through programs such as the Cadence Academic Network, which provides, among other things, access to technologies and online training, Purdue is able to procure the tools and IP it needs. Yet, even working on older processes with access to tools, the process for setting up a flow is daunting because of some key barriers: Most educational IP is limited to 130nm and above and full access requires the right relationships From a legal standpoint, there are a considerable number of license agreements to maintain Looking at the flow, most ASIC IP arrives with little instruction and typically almost no support, and the flow must be developed and de-risked before proceeding with fabrication There are also IT considerations, namely that modern ASIC design needs considerable compute power Refocusing on Research and Education “I feel we need to refocus on research and education,” said Swabey. “We’ve got this huge industry cost…but we have to stop spending time on these infrastructure problems and focus on research and education.” What this approach translates into is high-value learning from project-based activities, such as node evalution and analysis or designing on a power budget. “It would be awesome to have virtual machines in the cloud with the IP, flow, and tools setup,” Swabey said. And, he added, educational licensing from the industry certainly would go a long way in establishing teaching labs. Christine Young![]()
![]()
↧