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Cadence at DAC: Experts, Presentations, Lunches...and Denali Party Instructions
Cadence is doing a lot at DAC as usual. Here is a summary. But read it carefully, because some things you can't leave to the last minute. You need to sign up or you may be disappointed. In particular,...
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Cadence Online Support—Empowering Learning! New Learnings—Sigrity 2016
Cadence Online Support Features Setting up ‘My Alerts” The My Alerts section displays a count of the new content items added. This is generated taking into account your notification, search and...
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CDNLive EMEA: Do You Know What a FIT Is?
ADAS changes everything about automotive and requires a whole new range of skills in the automotive ecosystem that they have not had before: video and image processing, deep learning, high-bandwidth...
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Can You Trust Your IoT Supplier?
A few weeks ago, Nest announced that it was shutting down Revolv. You probably don't have a Revolv product, a sort of smart-home hub. It contains seven radios and so speaks almost any protocol of any...
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EDPS Cyber Security Workshop: "Anything Beats Attacking the Crypto Directly"
Many of the security breaches that you read about are the results of software failures such as buffer overflow. But hardware is also vulnerable to attack. After Chris Eagle's keynote , the rest of the...
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When Resources Are Limited, How Can Universities Teach Advanced-Node Design?
It’s an ongoing challenge faced by universities across the globe: How to teach advanced-node design to the next generation of SoC engineers when budgets are tight and access to the latest tools and...
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Cadence Presenting Four Spectre RF MicroApp Papers at IMS2016, May 22-27
Hello Spectre RF Users, Next week is my all time favorite technical conference - the International Microwave Symposium IMS2016 , May 22-27 in San Francisco, CA at the Moscone Center. If you're at the...
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CDNLive EMEA: Memories Are Made of This
At CDNLive in Munich, Amjad Qureshi talked about High-Speed DDR and LPDDR Memory Sub-system Challenges . Amjad is Cadence's VP of R&D for memory interface IP, so he and his team have to live with...
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Whiteboard Wednesdays—Modular VIP Architecture
In this week's Whiteboard Wednesdays video, Liron Stoler describes how Cadence Verification IP (VIP) developers strive to provide VIP in a useful and consistent manner. (Please visit the site to view...
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Party Like It's 1999—How the Denali Party Started
As everyone in EDA knows, Denali threw a party at every DAC for what seems like forever. It is actually since 1999 which, in EDA years, is pretty much the same as forever. When Cadence acquired Denali...
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It's HOT in Austin in June
Every DAC, Heart of Technology (HOT) organizes an event. This year it will be held on Monday, June 6, from 7:30pm to 11:30pm at the Speakeasy (412 Congress Avenue). This year's event will be benefiting...
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Linley IoT Conference: Security and...Well, Just Security
Mike Demler gave the keynote at the Linley IoT conference a couple of weeks ago. He is a senior analyst there, and also a senior editor of Microprocessor Report and Mobile Chip Repor t. His background...
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What Is RocketSim? Why Did Cadence Acquire Rocketick?
I talked to Uri Tal last week, who has just joined Cadence as a result of the Rocketick acquisition. Prior to the acquisition, he was Rocketick's CEO. He gave me a little history. Rocketick started...
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Making Rigid-Flex PCB Design a Little Easier
We now almost take for granted that computing power can be wrapped around our wrists or worn on a chain as a necklace. An array of wearable, mobile, military, and medical devices now rely on flex and...
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CDNLive: Routing at 10nm
At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence reported on what it took to pull together a version of Innovus Implementation System and a version of the ARM...
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Whiteboard Wednesdays—Creating an Acceleration-Ready Simulation Environment...
In this week's Whiteboard Wednesdays video, Ofer Steinberg explains how accelerated VIP can dramatically speed up verification and describes a method to simplify the application of a SystemVerilog UVM...
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Simulation Acceleration—Maximizing Simulator Performance
"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to describe a verification environment in which the Device Under Test is synthesized and runs on the emulator, while the...
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Continued Strength of the Design&Reuse IP-SoC India
Design&Reuse events are always exciting for their draw of an IP-centric audience. This year’s event was held in Bangalore, on April 6 th , and drew over 130 attendees. Experienced IP providers,...
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Andrew Kahng on Industry-Academia Cooperation
At CDNLive Silicon Valley, Professor Andrew Kahng of UCSD gave a presentation titled Toward New Synergies Between Academic Research and Commercial EDA . The paper won the best paper award for the...
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What's Good About the Latest in ADW? The 16.6-2015 Release Has Several New...
With the Allegro Design Workbench (ADW) 16.6-2015 release, you’ll have several new capabilities that enhance your productivity. Read on for more details … ADW Server Error Logging and Notification The...
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