At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence reported on what it took to pull together a version of Innovus Implementation System and a version of the ARM physical library that would work cleanly at 10nm. They titled their talk Routing at 10nm, Challenging but Achievable With Collaboration . There are a lot of moving parts in a design like this, with EDA tools from Cadence, standard cells from ARM, the foundry. That is before adding in other IP, and let's not forget about the system/SoC company actually doing the design. So what's new at 10nm? There is, of course, the usual fact that designs get larger, which stresses the tools more, especially since computers don't keep getting significantly faster every couple of years to bail us out. So what are the other changes at 10nm? Shrinking geometries, obviously, but also the fact that not all rules shrink proportionally There continues to be an increase in complexity of design rules (up 3X since 28nm) New multi-patterning rules since 16/14nm Full color flow, including in standard cell LEF and GDS streamout Increased pin-access challenges due to 1D routing requirements Metal1 could be double or triple patterned Increase in double patterned layers since 14/16nm Vias now need to be multi-patterned (thus color-aware) New floorplanning and placement challenges such as color-aware placement New endcap cells and other artifacts placement needs to handle These changes, in turn, translate into requirements (aka challenges) for the EDA tools, primarily Innovus Implementation System, and for the standard cell provider (ARM, in this case). For Innovus Implementation System, one big challenge is that design rules don't always map from the DRM (design rule manual) to the LEF for the routing world. Indeed, to support some of them, there are additions to the LEF syntax. Plus, code needs to be written to handle the new placement requirements and the automatic generation (autogen) of vias in the color-aware environment. Of course, that means, inevitably, working with early versions of the code, buggy versions of the code, and living with limitations until the code can handle them. Meanwhile, on the physical library side there are challenges. The first is to interpret the complex DRM and turn that into a standard cell architecture. Then, those cells need to be passed through unstable versions of Innovus Implementation System as the code just described is being written concurrently. Ultimately, a standard cell library is only as good as the results after place and route. There are a couple of new LEF constructs. It is a level of detail too far to describe them fully here, but the keywords are WITHINFIRSTWIDTH (which are rules for via enclosure) and THREECONCAVECORNERS (which are rules for specific situations to improve DFM). The whole handling of vias is different at 10nm. Some via structures are described in the LEF explicitly, and some are autogenerated. On top of that, for clock and power, due to the high currents, there are NDR (non-default rule) via structures. The end result: Number of Innovus violations reduced from around 20 types to 0 Runtime reduced 20+% DFM scores improved 30_% Correlation between DRM/router and signoff DRC reduced from about 20 types down to 2 Many CCRs closed Latest LEF syntax used for 10nm tech LEF 10nm nanoroute automatic via generation Of course, neither ARM nor Cadence actually builds SoCs (except for the Palladium emulation platform, in Cadence's case). The result of all this work means that there is a library and a flow for customers to do 10nm designs. Previous: What Is RocketSim? Why Did Cadence Acquires Rocketick?![]()
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