The adoption and usage of advanced node technology (16nm and below) has been extraordinary over the last few years. However, along with the benefits in power and area, the new nodes also contain new challenges when it comes to properly determining the variation caused by the smaller geometries. Much has been written about the proper ways to physically implement a FinFET design, but less has been written on the need for accurate variation analysis using some sort of statistical sampling. For most of these applications, due to the fact that they are usually designs that must meet their targets past the traditional 3-sigma boundaries, standard Monte Carlo simulations would take far too long to be able to provide accurate results. So, new mathematical methods have emerged to help solve this problem. The two competing methods are High-Sigma Monte Carlo (HSMC) and Scaled-Sigma Sampling (SSS) which is the preferred method used by Cadence’s Virtuoso suite of tools. The accuracy of the HSMC method strongly depends on the accuracy of the underlying response surface model, which is created first and then used to select the Monte Carlo samples to be simulated. If the response surface model is biased, the wrong samples could get selected for simulation and the results could be completely biased. The initial response surface model is built using a very limited number of samples out of hundreds of millions or even billions of possible samples. In most cases, these initial samples come from the area encompassing the normal working condition of the design. We have found that the circuit behavior can be quite different around the mean as compared to the tail conditions. The response surface model bias may indicate a wrong tail region for subsequent sampling, causing significant inaccuracy. Scaled-Sigma Sampling generates a reasonably large number of samples in the actual failure region without making assumptions. These more predictive samples are then used to estimate the failure rate. By combining this sampling method with Cadence’s Spectre circuit simulator, we are able to provide an additional performance boost since the random number generation is efficiently handled within Spectre instead of having to be provided outside of simulator and then restarting the simulator with new values. We believe as a user, you will find that SSS method has the advantage over HSMC if one or more of the following conditions apply: High Dimensionality : The number of simulations does not increase with circuit size for Scaled-Sigma Sampling. For HSMC, the number of samples to build response surface model and the cost of handling a large number of parameters will significantly increase with number of devices. High Nonlinearity : The SSS method is proven to work particularly well with strongly nonlinear problems because of its very general assumptions. For HSMC, it is extremely difficult to build a response surface model when an output is a very complicated nonlinear function subject to a large number of statistical variables. Large Number of Specifications : For the SSS method, the number of simulations does not increase with number of specs. This is not the case for HSMC. Having a large number of specifications that need to be tested can overwhelm the HSMC method. Very High Yield : The SSS method has no difficulty handling arbitrarily large yield, including >= 6 sigma. For HSMC the problem of handling huge amounts of data becomes very difficult when the yield is near 6 sigma. For example, for a billion MC samples with 1000 variables, and each variable requires 8 bytes to store as a double value, the total amount of data is 8TB, which is beyond the capacity of a typical computer’s memory or even disk. Any operations with this large amounts of data will take significant time and hurt the program’s overall runtime. TeamADE is pleased to offer our customers a more detailed whitepaper on this topic that can be downloaded from here . We are also honored to include the world’s largest foundry endorsement of our technology. You can see the webinar here to understand more about the value they see in our methodology. This technology is available as either part of the Virtuoso Analog Design Environment GXL or with the Virtuoso Variation Option. If you are interested in more details about what Cadence can do for you in providing a comprehensive design flow for designing, implementing and verifying advanced node designs, please visit us at: Cadence Advanced Node Design SolutionImage may be NSFW.
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