CDNLive Bengaluru takes place over two days. But it is organized very differently from the two-day CDNLive Silicon Valley. The first day is dedicated to verification, the second day to implementation, both digital and custom/analog. As a result most people only come to one of the days. The presentations given over the two days should be available on the Cadence website in a couple of weeks. Welcome: Jaswinder Ahuja Jaswinder could almost repeat his welcome word-for-word from the previous day. He did point out that the invited keynote speaker, Balaji Kanigicheria, who was billed as founder and CTO of Ineda Systems, has just been promoted to CEO, but it has not yet been announced. You heard it here first, folks. Keynote: Vivek Mishra So few people come to both days that even the Cadence keynote is a repeat. It is the same slide deck. It is interesting to see two people with two different backgrounds put a bit of a different spin on the same presentation. When I was at Cadence before, I wrote some of the keynotes for various events and often presented them. It was always interesting to see someone else take my presentation and run with it. Vivek started by pointing out how advanced India is because if you Google "self-driving car" you get a huge number of references. It turns out that in India, a self-driving car is just a car you drive yourself, as opposed to coming with a driver. I will cover the Michal/Vivek keynote in more detail in a separate post. Keynote: Balaji Kanigicheria The invited keynotes both days were about internet of things (IoT). However, the emphasis was very different. Yesterday was Karthik Sankaran of the 51-year-old Analog Devices. On the other hand, Balaji's company, Ineda, is a startup headquartered in Santa Clara with over 140 R&D engineers in Hyderabad, right in the center of India. They have raised $46M from the likes of Qualcomm, Samsung, Cisco, and Walden International (founded by Cadence CEO Lip-Bu Tan, the organization's chairman). Their charter is to build specialized SoCs for the IoT market. "In the future, everything wil be connected and can be addressed," he started by saying. Not just smartphones or even cars, but appliances and lightbulbs. He talked about IoT2C and IoT2B. I think the terms originated with McKinsey as a parallel to B2B and B2C internet companies. Obviously IoT2C is the consumer IoT market and IoT2B is the business IoT market. The business market represents the big opportunity since the consumer ROI is not that good. But governments and business need to make use of IoT technology, so the action is all in those areas: smart factories, smart cities, smart farms, and the like. As Karthik said yesterday, the big opportunity is to transform business processes and enable new business models. Balaji said that there is a high barrier to entry for IoT. You can't do all that much at the device level, which means you are forced to get involved in connectivity standards and cloud infrastructure. Plus, of course, security is a big deal throughout the lifecycle of the device: design, manufacturing, while it is in use, even when it is decommissioned (to ensure private data cannot be retrieved from a discarded device). A major change is the contextual environment. Always-on sensing means high power consumption. To keep the power low, he feels a different scalable model of compute is needed. Another challenge is that today's cloud infrastructure is not designed for IoT. Hundreds of clouds, thousands of backhauls, tens of thousands of hubs, millions of smart objects. This is starting to be known as "fog computing" since it is much more diffuse, compared to the cloud model where everything is done in the cloud. He sees a variety of opportunity for semiconductors: Higher levels of integration Innovative processing architectures Security architectures (software alone is clearly not enough) IP for the various sub-markets Low power. When he was at AMD they were trying to get their processor from 75W down to maybe 5W. Then the smartphone came, an order of magnitude lower than that, so AMD missed it. IoT is another order of magnitude or two lower than that. Technology Update: Digital and Signoff Vivek returned to give the technology update for digital and signoff. Meanwhile in another room (where obviously I was not) there was the custom/analog technology update. One big change in the last 5 or 10 years has been the coming together of analog and digital. He remembers when there were customers where analog and digital were in separate buildings and so they didn't even talk to each other. Now there is a lot of mixed signal, perhaps 85% of all chips. Pure digital is driving down to 7nm and beyond. Pure analog is at 65nm and 90nm. Mixed signal is mostly around 28nm. Of course, this has driven a lot of tool interoperability. Analog and digital have a lot of different care abouts, but they also have PPA and turnaround time in common. The big change in the digital flow has been the US family. This doesn't just make use of massive parallelism, everything runs on common engines. The Genus Synthesis Solution uses the same placer as the Innovus Implementation System, for example, and they both use the same timing engine as the Tempus Timing Signoff Solution. At the high end, it is all about power since the transistors are pretty much fast enough if you can get under the power envelope. Looking to the future, to 7nm and 5nm, Vivek talked about the need for full coloring (and color-aware placement). He also talked about the 5nm test chip developed with imec. This was announced my first day at Cadence and so was the first blog on Breakfast Bytes, after one where I introduced myself. Cadence is now the PPA leader with their implementation flow, and is continuing to invest to keep it that way. Yield Improvement Analysis Preet Yadav of NXP presented Accelerating In-depth Yield Improvement Analysis on Advanced Nodes Using Virtuoso ADE Product Suite . Actually, he called it Maestro, but that is an internal name so we'd better use the real name of the product. On-chip variation has become critically important beyond about 40nm. Dealing with it is important for a number of reasons: The variation is non-intuitive and so the worst case is not always where you think it is. For example, the typical corner might not lie between the SS and FF corners Variation changes as chips age and so the worst case can move If you are not careful, you are forced to trade off yield for performance. Push the performance too much and you will lose yield (and with it, of course, money). Virtuoso ADE Product Suite is the combination of three (comparatively) new products: Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier. Preef gave some motivations for moving to the suite from various flavors of Virtuoso Analog Design Environment (ADE), primarily that you can't perform Monte-Carlo analysis, which is the foundation for dealing with the yield impacts of variation. Sizing the design over the worst-case corners improves yield. One of the most powerful weapons in the arsenal is the Virtuoso Variation Option (VVO). Key features are: It provides advanced statistical analysis features Useful especially at advanced nodes Analysis focused on high-sigma designs Key features: mismatch contribution analysis, yield verification, fast statistical corner creation, high-yield analysis With the above flow, and especially using Virtuoso Variation Option, detailed analysis can be done with the Virtuoso platform easily, thus improving yield, and not at the expense of performance. His final conclusions: It is simple to move from Virtuoso ADEL/ADEXL to Virtuoso ADE Product Suite Iterations are simplified with the new Virtuoso flow Big time savings (many fold) are achievable with the new Virtuoso flow Detailed yield analysis can be achieved with the Virtuoso Variation Option A quick way to gather and analyze yield-impacting data Aging and Self-Heating Hany Elhak of Cadence presented Reliability: Accounting for Device Aging and Self-Heating in Advanced Nodes . All transistors age and all transistors self-heat. But we used to not worry about it. The heating effects were minimal and didn't really affect performance. The aging effects were small enough that, effectively, transistors lasted forever. But after 28nm, aging started to become an issue. And in FinFET processes, self-heating became a much bigger problem. The two problems interact, too, since temperature affects aging. Hany went into more detail and explained the Cadence solution to dealing with the problems. I will cover this in detail in a separate post. What's for Breakfast? While I was having breakfast on Tuesday here in the CDNLive hotel, we made the first of what is planned to be a weekly video called "What's for Breakfast?" giving a preview of what is coming up in the following week on Breakfast Bytes. Enjoy. (Please visit the site to view this video) Next: 5G, Coming Soon to a Phone Near You Previous: CDNLive Bengaluru: Day 1![]()
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