At CDNLive Boston, I moderated a panel session on signal and power integrity with a panel of five true experts on the topics. They work on some of the highest performance systems out there. It was a double-length session, taking up two slots at the end of the day. The four customers spent about ten minutes each going over their position on some aspect of power integrity and signal integrity. We did a little advance planning and made sure that they picked different areas to discuss. Then Ken Willis, from Cadence, discussed how Cadence's signal and power integrity tools stood up to the challenges, and what challenges remain to be overcome. The panelists were: Istvan Novak—senior principal engineer at Oracle Kevin Roselle—senior staff engineer at Qualcomm Dale Becker—chief electronics packaging engineer at IBM Stephen Scearce—senior manager of high-speed design at Cisco Ken Willis—product engineering director of high-speed analysis products at Cadence Istvan Novak, Oracle Istvan kicked off. His chosen topic was DC-DC converters. First, there are lots of things to like about them: They are small and efficient They work across a wide range of input/output ranges They work across a wide range of loads But they come with their own set of challenges. First, they are efficient, so they create strong switching noise and high-frequency burst noise. They are small so we can put them anywhere, but then they inject noise directly into sensitive circuits. Although they work over a wide range of input/output ranges, they may have compromised performance at some points in the range. Although they autotune and adapt to various loads, they may have inconsistent behavior. Debugging them can also be a nightmare. Stephen Scearce, Cisco Next up was Stephen, who focused on DDR4 challenges and advanced bus analysis. He talked about the issues of power, system implementation, crosstalk, and static timing post-route. He came up with a list of potential improvements: S-parameter quality for post-route time-domain simulations and SPICE convergence Include crosstalk effects in post-route simulations including PDF, not subtraction from margin Include power and return current effects in post-route simulations instead of having a separate flow AMI/statistical flow not standard in tools for single end signal, typically no models available Flows that facilitate statistical combination of jitter components and corresponding PDF and power spectral density Kevin Roselle, Qualcomm Echoing one of the points Stephen had made, Kevin focused on IBIS-AMI modeling for single-ended signals (such as DDR4 controllers to memory). He pointed out the problems of modeling with the line-conditioning equalization circuits such as FFE, CTLE and DFE, combined with the need to meet an eye mask with a very aggressive bit error rate. It requires millions of bits to get enough data for analysis. In a multi-vendor environment, it gets still more complex since different vendors have made different choices on how to support DDR equalization (or, in some cases, not even done that). But models need to be interchangable. His final pleas as for an official model: Dale Becker, IBM Finally, the last of the four "cases for the prosecution" was Dale. He has a different type of position from the three preceding engineers, since he works as part of the OpenPOWER organization, which is chartered with supporting vendors other than IBM using the power architecture. There needs to be a way to efficiently demonstrate compliance. The common way is to use time-domain simulations. But IBM has been working with Cadence to implement frequency-domain compliance checking. His biggest challenge is that when you put the whole system together, between chips, and boards, and packages and connectors, he ends up with eight components from eight different suppliers and eight different design teams. Of course, the PCB comes last since you can't design the PCB until the other components are ready. You can see the complexity in the above diagram. He looked to the future, where it gets even harder: DDR5 Broader use of high-speed optical interconnect NRZ data rate limits PAM4 (four-level pulse amplitude modulation) He felt the need for more standardization for IBIS, IBIS/AMI, SPICE, key eye parameters, insertion loss, and more model parametrics Ken Willis, Cadence Ken Willis complained that after ¾ hour of customer challenges, he only had 10 minutes to respond. But he managed to ignore the "5 minutes left" signs and took the best part of ½ an hour to talk about where Cadence could help, which pitfalls remained, and potential workarounds. I won't try and summarize everything he said. He had more information than can easily be summarized in a single blog post. One area in which he went into a bit of detail was which compliance kits for serial link standards already exist: SFP+ HDMI 1.4 and 2.0 PCI Express Gen3 (with Gen4 coming soon once the standard is finalized) 10GBASE-KR USB 3.0 and 3.1 (Gen 2) MIPI MPHY OpenPOWER P8 PCIe3 Automotive Ethernet 100BASE-T1 Since no discussion of high-speed serial interface modeling would be complete without an eye-diagram, Ken also showed an example of PAM3 and PAM4 modeling: Q&A from the Audience For the Q&A part, we did something new. The CDNLive App allows questions to be asked in the App, so the audience could queue up questions (and even vote them up if others especially wanted to hear the answers). One subtlety was that the panelists could discreetly enter questions for other panelists. Since I was moderating the panel session, I couldn't take notes, so I'm not going to try and attribute all the comments to each participant, nor to cover everything that was said. So the first question was what changes people expected to see in the next two or three years. Everyone felt that the bounds were being pushed, especially as the industry gears up to understand DDR5 and what needs to be done. There is a steep learning curve, but the tools are there. Education is a challenge. More serial link analysis is needed, and it would be great to get simulations into the cloud so we can do more. There will be pressure on interconnect extraction detail since we need full-wave accuracy. But we need to work out how to selectively apply to certain structures so we don't bog down the whole methodology. With DDR buses before, we've packed things in as tight as we can, sprinkled in some grounds, maybe checked cross-talk. But it's a bit of a paradigm shift if we keep going up to 4Gbps with single-ended signals. What about interference between serial links and parallel bus structures on the same chip? Power distribution is the big problem: how you balance it and how you control the switching noise, and then how you stop that noise from propagating into other IP on the device. Might be an IC, or a package, or even board level. There are examples of crosstalk going across a module because of holes in the planes and so forth. So having single-ended signals and differential pairs going through the same drilled area in the package will be a problem, and as we start having 56Gbps PAM4 there is going to be learning in the industry about what some of those propagation effects are, even at the board level. We talk a lot about SI and PI, but we don't hear much about EMI in simulation. What's the panels experience solving EMI problems? A lot of the things we do to improve the power integrity also improve the EMI issues. Many people think about compliance, but that's a long way from what we have in our systems. EMC is a compliance issue. But what we see now is that what used to be long-distance interference is now becoming more and more short-distance. For example, we had a design where moving the AC/DC power supply around without changing the wires made a difference; adding jitter showed that the radiation from the AC/DC power supply was the reason. This was all happening in our own box. So not the traditional EMC problem that people are trained for, it is something closer range and more complex. The other major shift I am seeing is that more and more and better and better models are needed. Luckily they are in the making even if they are not available yet. Whether it is DC-DC converters, passive components, or active components, the model complexity is exploding. A huge improvement is on the way. We are seeing EMI in the basics. Routing over splits, failing to shield the edges of boards. So I think a lot of our EMI problems result in bad power design, or bad SI and PI. If we apply the tools that are evolving from practices that we can see as a result of simulations on the SI/PI side. We need to beef up the DRC, and that can take some of the first-order issues off the plate. There are just so many components, so many vias, and so on. It is worse still in automotive. Not just the boards but the cables, which are spatially located near the frame. So that needs to be another area in the simulation space. If you have your EMI guys just in the compliance area, then the risk is that the first time you find a problem is after you’ve built the system. Another question was about the range of timing improvements seen with CTLE and FFE in DDR4 systems. These channels typically are not loss dominated, and CTLE and FFE are really good for lossy connects. We are finding the real issues are ISI and crosstalk, and power distribution stuff. With multiple DIMMs in a PC-type environment, it is unclear how much equalization really helps. You have multiple loads, two ranks per DIMM. We have found that with mild equalization we can improve things…there is a minor improvement. Low 10s of picoseconds. The IP vendors come and say look, we have all this equalization, but we find that under certain conditions it does help, but it’s not huge. More equalization is not always better. What about soft turn-on circuits and VRM noise? It certainly helpls and it has a long history. So the short answer is ‘yes, it helps’. Longer answer is a warning. There is no power transfer without power loss. Can get close, currently around 90% efficiency for DC-DC converter. Soft switching definitely helps significantly in many areas. And what about simulation moving into other areas? Well, more accuracy, but also thermal, not just SI and PI (and EMI). With that, the band started up next door, the bar opened, and so we called it a day. Thanks to all the panelists for their contributions. Eventually the presentations will appear on this page . Previous: Are These Codecs Any Good? Netflix Tests Them![]()
![]()
↧