(Please visit the site to view this video) Monday: A preview of DVCon Europe on 19th/20th October, where Cadence is presenting 3 tutorials and several papers. Tuesday: At the Linley Processor Conference, Krste Asanović presnted the RISC-V ISA and then Markus Levy played devil's advocate about open ISAs. Wednseday: Cache-coherency is the new normal. A summary of 3 new announcements of cache-coherent interconnect from the Linley processor conference. Thursday: Highlights from MemCon, which will have taken place earlier in the week. Friday: How to verify MIPI protocols. Cadence has a lot of experience in this area and shared some of it at the first MIPI DevCon.Image may be NSFW.
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Clik here to view.
