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What’s for Breakfast? Preview October 10th to 14th (video)
(Please visit the site to view this video) Monday: A preview of DVCon Europe on 19th/20th October, where Cadence is presenting 3 tutorials and several papers. Tuesday: At the Linley Processor...
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Cadence Implementation Flow for an ARM Cortex-A73 at 10nm
Increasingly, taking an appropriate ARM ® processor has become the standard way to pipe-clean a digital flow in a new process. ARM processors are widely used and are available at various levels of...
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The Industry Vision for Portable Stimulus
As I mentioned in my last blog post , portable stimulus is one of the main areas of focus for me at Cadence. Paul McLellan has published two excellent posts about Perspec System Verifier, our product...
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DVCon Europe Preview
DVCon Europe in Munich is coming up on 19 and 20 October. For any Americans reading this and thinking October in Munich means Oktoberfest and beer, I hate to disappoint you. Despite the name,...
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3 Key Trends in Safety Design for ADAS—TSMC OIP Ecosystem Forum
Vehicles with varying levels of autonomous driving capabilities are logging millions of miles on roadways. Still, a new survey, released recently by the Kelly Blue Book auto information service , finds...
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RISC-V: the Case For and Against
At the Linley Processor conference recently, there was a presentation about RISC-V from Krste Asanović, who is the leader of the team that defined the RISC-V ISA at UC Berkeley, and is currently on...
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Ultra-Wide-Band Workshop for Balkan Countries
Countries which were founded after the collapse of Yugoslavia have long tradition in microelectronics. Due to import limitation during the time of Iron Curtain, Yugoslavians had to be inventive. As a...
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Welcome to the Signal Integrity and Power Integrity Community
This is your resource for all things regarding Signal Integrity and Power Integrity solutions for PCB and IC Packaging. In these blogs, we'll focus on: Introducing new solutions and features Tech Tips...
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Whiteboard Wednesdays - Driving Forces and Design Concerns Behind PCI Express...
In this week's Whiteboard Wednesdays video, the second in a two-part series, Lana Chan explores the factors that drove the development of PCIe Gen4. She also details SoC concerns that design and...
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Cache Coherency Is the New Normal
You hear a lot about cache coherency these days. In fact, at the recent Linley processor conference, no fewer than three companies announced new cache-coherent networks-on-chip (NoCs). Caching The...
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What’s Good About Allegro PCB Editor Backdrill Capability? New Capabilities...
The 17.2 Allegro PCB Editor has improved backdrill capabilities. Backdrill data is now stored in the library padstacks and utilized at the design level during the analysis and backdrill generation...
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MemCon 2016: Storage Class Memory
MemCon, the annual all-things-memory conference originally started by Denali and since continued under the Cadence umbrella, took place at the Santa Clara Convention Center this past Tuesday. The...
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Why You Should Never Use 2.5D for Characterization at Advanced Nodes
Parasitic extraction is a critical piece in design signoff. It translates geometry information such as wires and shapes into electrical properties such as Rs and Cs. Together with analysis technologies...
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What’s for Breakfast? Preview October 17th to 21st (video)
(Please visit the site to view this video) Monday: GLOBALFOUNDRIES announced new nodes on their process roadmap. I take a look. Tuesday: One of the new GF processes is 12FDX, an FD-SOI process. Last...
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How to Verify MIPI Protocols
At the recent MIPI DevCon, Cadence's Ofir Michaeli gave two presentations on verification. The first was Effective Vertification of Stacked and Layered Protocols . Then he was back later in the day to...
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Virtuoso Video Diary: Creating Net Groups and Constraining Them with Spacing...
In this new age of complex designs and scaling of technology nodes, there are more number of wires per given square unit of area. As a result, applying constraints is considered wise to make sure...
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GLOBALFOUNDRIES' Dual Roadmap
The Story So Far GLOBALFOUNDRIES had a 28nm process Hi-K PolySi process. I think that even they would admit that they were late to market with it. They also announced that they were licensing 28nm...
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Silicon on Nothing: the Origins of FD-SOI
Yesterday, I wrote about the new 12FDX process, which is a derivative of the original 28nm FD-SOI process developed by ST Microelectronics. Last year I talked to Thomas Skotnicki. He is the father of...
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3 Reasons That the Semiconductor Clouds Are Gathering
With cloud technology going vertical, everything is changing. The world is connected like never before—managing and processing large amount of data, every single second. Augmented/Virtual Reality is...
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Whiteboard Wednesdays - Error Injection: Predefined and Callbacks
In this week's Whiteboard Wednesdays video, James David talks about the benefits of two types of error injection, predefined and callbacks. (Please visit the site to view this video)
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