Parasitic extraction is a critical piece in design signoff. It translates geometry information such as wires and shapes into electrical properties such as Rs and Cs. Together with analysis technologies including simulation, timing, and EM/IR tools, parasitic extraction provides assurance that your design is ready to move ahead to production. Yet, advanced nodes bring new parasitic extraction challenges stemming from technologies and techniques such as FinFETs, stacked die, and multiple patterning, as well as from systematic and random variations. Smaller processes also add complexity to layout styles. There are simply more layers to consider and also more co-planar layers (like in FinFETs) that need to be modeled differently from an extraction standpoint. Simulation is affected, too, as characterizing FinFET SPICE models, for instance, is much more complicated than characterizing traditional SPICE models. In the face of these challenges, 2.5D pattern matching technologies are increasingly demonstrating a lack of accuracy that’s needed at smaller processes. 2.5D tools pre-characterize small building blocks offline; at runtime, they perform matching with the small building blocks. While the building blocks are accurate, the real layout is not an exact match, so modeling needs to be done. Essentially, translating the real layout into a combination of small building blocks presents a performance gain, but accuracy takes a hit. However, this is the only way to make the tool run for large chips. So in the end, designers using 2.5D tools are forced to trade off between accuracy and performance, and have to make unnecessary compromises. Can you really afford to leave performance on the table? 3D vs. 2.5D Tools Market pressures continue to push more organizations to ramp up on advanced nodes as quickly as possible. To generate the original spec, foundries initially examine circuit performance with each new process. As the critical link to translate shape and geometry information to electrical conductivity characteristics like capacitance and resistance, extraction gets impacted immediately, as processing challenges on the foundry side translate into modeling challenges on the extraction side. 3D field solvers are more accurate than 2.5D tools but run more slowly. And the point of moving to advanced nodes is to design chips that run faster. But the same margin 1% loss on mature nodes could be a 10% loss at advanced nodes. If you don’t want to bear this level of loss, you might choose to run a field solver, sacrificing the turnaround time for greater accuracy. Where You Could Be Sacrificing Performance Here are a few key designs where the performance sacrifice that comes with using 2.5D pattern-matching tools is proving to be detrimental: Memory (DRAM): It’s not easy to model and capture all of the effects in these designs using 2.5D technology due to their complex tall vias, which are 3D structures SRAM/bitcell: Compact designs with complicated coplanar wiring can lead to parasitic extraction inaccuracies of critical bit lines and word lines. These have very repetitive structures, so it is possible to use a field solver to solve a unit and then stitch units together to form a circuit. But the challenge comes when you have to make certain assumptions on boundary conditions. Stitching together bitcell units also results in an accuracy loss. Library and intellectual property (IP): Requires fast runtimes and low memory usage for full cell and library characterization, though high accuracy is needed to ensure deterministic results of characterization that is reused multiple times. This leads to a performance/accuracy tradeoff, where project deadlines often determine what is sacrificed. Touch display and LCD/TFT: Non-Manhattan shapes require an accurate parasitic extractor, as well as faster runtimes for full-chip signoff extraction. Traditionally, designers have used silicon measurements, but this approach takes months. TCAD technologies are also used, but they are slow as well. The Market Needs a New Kind of 3D Field Solver As shown in the figure below, the 2.5D and 3D parasitic extraction tools market currently consists of: Finite element method (FEM)/boundary element method (BEM) tools (3D), which use numerical solvers to model the problem. These are typical deterministic solvers, which mean the calculated results are the same from run to run. The fundamental challenge of these tools is proper meshing. In designs where the ratio between the smaller feature size and the larger geometry size is too big, numerical instability could result and, in turn, extend the time to convergence. As such, these tools are ideal for smaller structures. Random walk field solvers (RWFS) (3D), which use a statistical way to model the same numerical equation as BEM tools. The advantage of this kind of solver is that it does not require exact meshing; therefore, it is less sensitive to problems that emerge with small and large geometries. Pattern-matching tools (2.5D) Clearly, what’s needed is a 3D parasitic extraction tool that provides the high accuracy, high performance, and high capacity needed at advanced nodes. The market is more than ready for the next generation of 3D field solvers. Christine Young P.S. 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