The Story So Far GLOBALFOUNDRIES had a 28nm process Hi-K PolySi process. I think that even they would admit that they were late to market with it. They also announced that they were licensing 28nm FD-SOI from ST Microelectronics who developed it, and I think everyone assumed that they would run the process at least partially as a second source to ST, but a year or two after announcing the licensing, there was still no further announcement. There were rumors that they were skipping 20nm and were developing a FinFET process internally around the 14/16nm node when, to everyone's surprise, they announced that they were licensing Samsung's 14nm FinFET process. Then, a second surprise, when about a year ago they announced that they would not have a 28nm FD-SOI process, but were creating a more aggressive 22nm version called 22FDX (actually there were four variants of the basic process). See my previous posts GLOBALFOUNDRIES Gets a 14nm Process and GLOBALFOUNDRIES FD-SOI, Yes It's True . 14LPP is the mainline 14nm process, there is also an LPE where the E stands for early, but that is only used for a single product. The defect density is giving mature yields on volume production. They are manufacturing many products including very large die. There is a strong IP portfolio, in particular with foundation IP designed by INVECAS just for them (as opposed to being designed for some other process and ported to the GLOBALFOUNDRIES process). There will be extensions in both the IP portfolio and some process and qualification changes for automotive. They plan a 7.5T standard cell library, too, for still higher density. One of the question marks about 22FDX is whether it is getting traction. There are over 50 customers engaged, many of them coming from 40nm (and above). The value proposition of the process is close to FinFET performance, but at 29nm die cost. It is also very low power, with operation down to 0.4V and leakage of 1pA/um. In addition, there is software controlled body-bias that can control power versus performance. For more details on body bias, see my post Cadence Tool Suite Qualified for 22FDX Reference Flow . The basic process architecture is also very attractive for RF integration. Now This Week's Episode, Read On... A month ago, on September 14, they announced the next step on their roadmap. Well, since it is a dual roadmap, it is really two steps. If you don't have time to read more than a few words, the two-bullet summary is: 7nm FinFET 12nm FD-SOI 7nm FinFET Very little information about 7nm was announced. At this point they are just announcing that the 14nm roadmap skips 10nm and goes straight to 7nm. Most details are being left for a later date. 7nm is a process developed internally (remember, 14nm was licensed from Samsung), presumably by many of the process engineers that came on board with the IBM Semiconductor acquisition. The logic density will be 17M gates/mm 2 and the performance promises an uplift of at least 30% from 14nm, with A72 performance at over 3.5GHz. The power reduction versus 14nm is over 60% (presumably at the same clock speed). The process is targeted at people who want performance and density at any cost, which would be the server market, networking, graphics, and high-end mobile. There are up to 17 layers of metal, high-speed SRAM, compatibility with EUV if and when it arrives, and compatibility with 2.5D and 3D packaging. The process will run in Fab-8 in Malta (upstate New York), with production ramp in 2018. 12FDX There are three questions that get asked all the time about FDX: Is there an ecosystem? Is there a roadmap? Is there a second source? At the same time as 12FDX was announced, GLOBALFOUNDRIES also formalized the ecosystem around FD-SOI with an initiative called FDXcelerator. This consists of a number of partners in EDA, IP, ASIC, design services, and more. Cadence is one of the initial contributing partners. The biggest motivation is to lower the barriers of migration from bulk nodes such as 28nm or 40nm. So that answers question #1. Question #2 was addressed by the 12FDX announcement. This is a process targeted at cost-sensitive markets where FinFETs deliver more performance than is needed, or at least than the price point will support. The energy efficiency is very high with sub 0.4V operation. The power is less than half that of 14nm FinFET. The reason to go to 12FDX rather than 10nm or lower is to keep the mask count down by avoiding triple and quad patterning. There are 40% fewer masks than 10nm FinFET, for example, but it is still a full node shrink from 22FDX. Another big differentiator for 12FDX is that wireless connectivity can be on the same die, with the highest fT and fMAX of any process. This is due to planar devices, which have lower parasitics than FinFETs. 12FDX will run in Fab 1 (Dresden, Germany), although it will require some lithography upgrades. There was no announcement about question #3, a second source, but strong hints that there would be one. Watch this space. eMRAM Another announcement was 22FDX eMRAM. This has 1000X faster write speeds and 1000X higher endurance. It is scalable beyond 22nm and there are plans to make it available on both tracks of the roadmap, presumably meaning at least 14nm FinFET and 12FDX. This is especially important in ADAS and vision processing (but I repeat myself). So, putting it all together, here is the roadmap in a single diagram: Smallest Transistor Ever Nothing directly to do with GF, but a team of researchers at UC Berkeley (including Chenming Hu, father of the FinFET) have announced the smallest transistor ever. It's a 1nm gate, although I can't tell whether that means the gate is 1nm across or whether it means it is the next step on the 16/10/7/5 node progression, which bear no resemblance to any measurement on the silicon. The paper is gated so I can't actually look at it. But Science Bulletin has a piece about it . Oh wait, it reports that "electrons flowing through silicon are lighter and encounter less resistance compared with MoS 2 ." I'm pretty sure the electrons are not lighter. And "the MoS 2 transistor with the carbon-nanotube gate effectively controlled the flow of electrons." I'm pretty sure the gate is not carbon-nanotube, that would be the channel between the source and the drain. I'll wait for the paper, it'll be ungated in a year... Previous: How to Verify MIPI Protocols![]()
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