At the largest gathering of formal verification (FV) engineers in the world, also known as the Jasper User Group, Ziyad Hanna gave the final presentation. Since this was on future developments in the Jasper product line, and since he is the VP of R&D, that was a cunning way to ensure that everyone stayed all the way through both days. Not only is JUG the largest gathering of FV engineers, Cadence has the largest R&D investment in FV, too, with several sites all over the world. Do you speak both Hebrew and Portuguese? JasperGold: "The Highest Quality Product in the EDA Industry" Henry Ford supposedly disparaged market research by saying that if he asked his potential customers what they wanted, they would have said "faster horses." Just as Yogi Berra (maybe) said, "I never said all the things I said," it seems Henry Ford never said that, but he did behave that way. His singular focus was to drive the cost of manufacture down through standardization and thus grow a large market. That worked really well—in 1921, Ford had 65% market share. But then people decided that they'd like more choices and better quality. By 1927, Ford's share was down to 15%. Verification is, perhaps, similar. If you ask verification (simulation) engineers what they want, they'll say faster simulators, not formal verification. But increasingly, formal approaches are more and more important. As Erik said in the opening day's keynote, "FV when you can, simulate when you must." So what do people want in formal and automated verification? Well, faster horses for a start. No matter what other features people might like, people need more scalability. They want to save time by running designs faster, but they also want to be safer. Every time you constrain the design to make the proof engine's life easier, you risk a false positive, where you tell the tool something that isn't true. They want more predictability, better debug, higher capacity—more of everything. One other thing that everyone wants is more enhancements. Since JUG 2015, there have been 1,640 new enhancements, which is a 29% increase on the previous year. Sometimes enhancement really means enhancement, sometimes it is a euphemism for fixing something that is broken. The weighted defect count for JasperGold has fallen by 36% since the start of the year. Ziyad is confident that "JasperGold is the highest quality product in the EDA industry." Incisive Formal When Cadence acquired Jasper, we already had a formal product called Incisive Formal. There is a saying about not switching horses in midstream, but now, outside of regression suites, it is approaching the time to switch. Incisive Formal will continue to be available and fully supported. But it will be bug fixes only after 15.2 earlier this year, and all new innovation will be on the JasperGold platform. This investment will be both in increasing the lead on core technology and increasing capacity and performance, but also strengthening links to other parts of the Cadence system and verification flow. Increasingly, as both keynote speeches during JUG emphasized, FV is no longer something only understood by one PhD in a back office, it is now a full part of any verification plan. The release roadmap is detailed in the above diagram. Scaling All the Things The big steps in JasperGold are: Analyze and elaborate Proof setup Abstraction Proof Debug Ziyad took a look at each of these in turn. Analyze and Elaborate These are the front-end compiler technologies that provide efficient analysis, elaboration, and synthesis LTL spec language compiler for scalability and completeness. Today, JasperGold's capacity is >100M gates. The target is 1B gates in less than two hours, and less than 100GB. That's thoroughbred performance. Proof Setup and Abstraction This includes automatic identification and analysis of clocks and reset, and computation of full-chip reset sequence. The roadmap here is 5X speedup of full-chip reset simulation, getting it below four hours. A relatively new development is formal-friendly assertion-based verification IP specification packages (ABVIP). The roadmap is more of the same: rapid adoption kit to allow users to quickly connect the ABVIP and get going, further integration with the formal scoreboard, advanced protocol debug (at the protocol level), and expanding towards "formal signoff." Proof JasperGold has the most powerful formal engines as measured by proof completion, bound depth, the number of proofs in parallel, and the memory footprint. The roadmap is faster horses. Reduce proving a task less than 10 hours, converge on and/or reach properties with around 10K flops in a reduced cone-of-influence. Converge on and/or reach >95% of the properties in under 10 hours and under 8GB per engine. Improve the average bound proof by 5% per year. And handle 500,000 properties per task. For many of the roadmap targets that Ziyad discussed, he had graphs showing the improvement over the last few years. He did this partly to show the progress that has been made but, perhaps more importantly, to show that the targets that he was talking about were not pulled out of thin air and were achievable. I'll just show one of them as an example, JasperGold Engines Convergence. This has already improved 50% since 2010 but with a goal of 95% reachability and 80% proofs, there is still plenty of way to go. It's all very well talking about faster horses, but sometimes you have to race them. There was a 2015 hardware model checking competition with about 20 entrants. Jasper outperforms all of them...and plans to stay that way. Visualize: the Leading Formal Debugger There are lots of facets to this: Quietrace, WaveEdit, trace manipulation and confirmation, datapath debug using graphs, and more. The roadmap is to add more scalability to handle long traces. The plan is also to boost performance of the interpreted simulator kernel and develop a compiled simulator, too. TL;DR Long posts on Reddit (and elsewhere) sometimes have a TL;DR summary. This stands for "too long, didn't read." So here is Ziyad's TL;DR summary for anyone who didn't have time to read the whole post: We believe we are ahead of competitive solutions We are increasing investment to extend the lead We know how to get there If you have ever listened to a company earnings call, it always starts with a safe harbor statement that the company is giving its best view of the future, but stuff happens. Each slide in Ziyad's presentation came with a little bit of small print, too: this slide contains forward-looking statements regarding Cadence's business or products, actual results may differ materially from the information presented here. Oz's Wrapup Oz wrapped up the user group meeting. There always seems to be a theme running through JUG, a different one each year. This year it was that formal is at the core of verification. "Use formal when you can and simulation when you must," as Erik said in the first hour of the conference. Even Oz agreed that was much better than saying formal is like yoga. He then went on to present the best paper award. I don't know if it was pre-planned, but there ended up being two "best" papers so that Jim doesn't win it all every year: Best newcomer: Anders Convery of ARM Best paper: Jim Kasak of Hewlett-Packard Enterprise Previous: RISC-V 5th Workshop Preview![]()
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