The 5th RISC-V workshop is coming up on November 29 and 30 on the Google Quad campus (468 Ellis Street, Mountain View, CA). RISC-V is pronounced "risk five", so perhaps we should just call it the Vth workshop. The preliminary schedule has now been published. For those of you who are new to RISC-V, you can read some earlier things I wrote: RISC-V: Instruction Sets Want to be Free RISC-V: Gathering Momentum RISC-V: the Case For and Against Or you can read RISC-V's summary in their own words: RISC-V is a new instruction set architecture that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the UC Berkeley. RISC-V has been an instant hit in academia since there is a lack of ISAs that make sense for pedagogical purposes. The most obvious architectures are x86 and ARM, but these are both too complex and come with legal complications. What I think is more interesting, and perhaps surprising, is the interest from industry and even whole countries. For instance, updates to Google's coreboot will not commit if RISC-V is broken, and India has decided to standardize on RISC-V as the national ISA. In the January workshop, there were 16 members of the RISC-V foundation, at the July workshop, 41, and now there are more. I expect we will find out the number during the workshop. The keynote on the first day will be given by Eric Grosse of Google on Security, Open Source, and Open Standards . Until recently he was the VP of Google's security and privacy team, but he has returned to hands-on work. From 6pm to 9pm on the first day, Google is hosting a reception at the Computer History Museum. Significant presentations at the upcoming workshop, just from what background knowledge I have, are: Presentations from Yunsup Lee, Arun Thomas, and Rick O'Connor about various aspects of the RISC-V foundation Krste Asańovic on the V vector extension proposal Jack Kang of SiFive. He told me when I interviewed him that they would have silicon by the end of the year. And he told me that they would be making announcements at the workshop. Perhaps they will be putting the Si in SiFive Neil Hand of Codasip. They have been a very early processor IP supplier to have product using the RISC-V ISA Farzad Fatollahi-Fard of Lawrence Berkeley Lab on HPC Brian Zimmer of NVIDIA. At the last workshop, they announced that they would design their own RISC-V-based control processor that would go in all future GP Steve Wallach of Micron, about 128-bit addressing and security Quan Ngyen of MIT on thousand core shared memory systems Derek Atkins of SecureRF on...surprise...security Alexander Redkin of Syntacore on a family of sythesizable cores Maxim Maslov of Esperanto on a fast instruction set simulator. I can't find anything out about Esperanto since they break my first rule of marketing which is to get the website with the company name. Especially important if your company is named with a word that produces a zillion hits in Google already Alex Bradbury of loRISC on RISC-V and LLVM (compiler infrastructure project—apparently the initials don't actually stand for anything any more) There are more, including lots of projects from universities, which are hard for me to tell how significant they are just from the titles. As I said above, the interest from academia is not surprising, so I focused in this list on the industry members Here is the full schedule for the two days. Or just go register . Previous: JasperGold: Thoroughbred Performance![]()
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