Soon it is the International Electron Devices Meeting. It takes place in San Francisco Hilton Union Square (which is actually not in Union Square but on O'Farrell Street a couple of blocks away). It is from December 3rd to 7th. So it starts next weekend. IEDM has such a strange name because it goes back over 60 years to a period when transistors were not really a thing, and the integrated circuit had not been invented. In the early years, an "electron device" meant a tube (valve in British English). By the way, for the foreseeable future, IEDM will be in San Francisco rather than its previous routine of alternating between Washington DC and San Francisco. One thing that I've noticed about IEDM is that on alternate years there are major announcements from the major semiconductor manufacturers and in the other years, no news. This is an on-year, with major announcements at 7nm from TSMC, and from GLOBALFOUNDRIES/IBM/Samsung. One takeaway from just the abstracts is that TSMC will not be using EUV, but the GF/IBM/Samsung consortium will, or at least can. These two papers are probably worth price of admission on their own. The only drawback is that you are not allowed to record the sessions nor take photos, and they won't be handing out the slides. So probably there will be tantalizing flashes of actual layer pitches, but too fast to write them all down. See later in this post for more details. This Year's Program As usual, IEDM is structured with different things on different days: Saturday 3rd: Tutorials on: Scaling BEOL Physical Characterization Spintronics Architectures for Neuromorphic Computing FEOL Reliability Embedded Systems for IoT Sunday 4th: Short Courses on: Technology Options at the 5nm Node (organized by imec, gotta put it all in lower-case to be correct) Design/Technology Enablers for Computing Applications (organized by NVIDIA, gotta put it all in upper-case to be correct) Monday 5th: Plenary Session: Technology Scaling Challenges and Opportunities of Memory Devices, Seok-Hee Lee of Hynix Brain-Inspired Computing, Dharmendra Modha of IBM Symbiotic Low-Power, Smart and Secure Technologies in the Age of Hyperconnectivity, Marie-Noëlle Semeria of CEA-Leti Monday 5th through Thursday 7th (after Plenary session): 7 or 8 parallel tracks of specialized topics Special session on Wearable Electronics and the Internet of Things (session 6) Special session on Quantum Computing (session 13) Special session on System-Level Impact of Power Devices (session 20) Special session on Ultra-High-Speed Electronics (session 29) Also there are receptions, evening panels, lunches and more Plus, for the first time, there is an exhibit area 7 Nanometer The two big late-news papers on 7nm are: Paper #2.6, A 7nm Platform Technology Featuring 4 th Generation FinFET Transistors with a 0.027µm 2 High-Density 6-T SRAM Cell for Mobile SoC Applications , by a huge team from TSMC A 7nm CMOS Platform Technology for Mobility: TSMC researchers will present the world’s first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring FinFET transistors. The technology can be optimized to emphasize either high performance or low power operation to accommodate the needs of diverse mobile applications. It features more than three times the gate density and either a speed gain (35-40%) or power reduction (>65%) versus the company’s commercial 16nm FinFET process. To demonstrate the technology, the researchers built a fully functional, low-voltage 256Mb SRAM test chip with full read/write functionality down to 0.5V, and the smallest SRAM cells ever reported (0.027µm 2 ). Key features of the 7nm technology are an advanced patterning technique used with 193nm immersion lithography, an optimized fin width and profile, a raised source/drain epitaxial process that strains the transistor channel and reduces parasitics, a novel contact process, and a copper/low-k interconnect scheme featuring different metal pitches and stacks . Paper #2.7, A 7nm FinFET Technology Featuring EUV Patterning and Dual-Strained High-Mobility Channels , by a huge team from IBM/Globalfoundries/Samsung A 7nm CMOS Platform Technology Using EUV Lithography: The 7nm FinFET technology to be disclosed by the IBM/Globalfoundries/Samsung technology development alliance is the first integrated platform technology to use extreme ultraviolet (EUV) light to pattern transistors. A long-anticipated development, EUV lithography may become a requirement for ultra-small devices because the wavelength of EUV light is much shorter than that of the light currently used (13.5nm vs. 193nm) and it simplifies patterning. Here, EUV lithography and other advanced patterning approaches have led to the tightest contacted polysilicon pitch (44/48nm) and metallization pitch (36nm) ever reported for FinFETs. The technology also features dual-strained channels on a thick strain-relaxed buffer (SRB) virtual substrate to combine tensile-strained NMOS and compressively strained SiGe PMOS for enhancement of drive current by 11% and 20%, respectively, versus a common planar HKMG process. It also features novel trench epitaxy to minimize the resistance of the highly scaled contact regions. These two papers are in session #2 at 3.40pm and 4.05pm respectively. The room will be full, I'm sure. Learn More Full details on all things IEDM are on their website here . Or just go straight to online registration . If you can't make it, I will be there for all 5 days (conveniently it is walking distance from where I live). Breakfast Bytes will have several posts during December. Next: Portable Stimulus Standard Previous: Happy Thanksgiving. Do You Have Toenailitis?![]()
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