At the recent IEDM in San Francisco, Coventor organized a panel titled BEOL Barricades: Navigating Future Semiconductor Yield, Reliability, and Cost Challenges . The BEOL, back end of line, is the metal, although where it begins and ends, as you will see, is debatable. The panel was moderated by Ed Sperling and the panelists were: Paul Besser of LAM Research Chih-Chien Liu of UMC Craig Child of GLOBALFOUNDRIES Anton deVilliers of Tokyo Electron David Fried of Coventor Kelvin Low of Samsung was meant to be on the panel but he had to be in China instead. The first question for discussion was where BEOL begins and ends. Craig went with "first metallization all the way up to the bumps" but he admitted that the boundary between middle of line (MOL) and BEOL is starting to blur with resistance becoming such a big issue. Anton pointed out that a buried wordline is a piece of metal in the middle of the line. In logic, nanowires will need buried metal, which is clearly MOL. It is also getting blurry on the back end since packaging is now the next way to scale with litho-imaged interconnect. The challenges of BEOL at 10nm and 7nm are mostly RC delay and reliability. But David pointed out that cost is a big issue since everything at the lowest levels needs to be done over and over again due to multi-patterning. If you add too much cost all the way up the stack, it rather defeats the purpose. Craig echoed this, pointing out that mask count is going through the roof. BEOL now has as many masks as the old entire stack, with eight masks for each via/line level, all critical. The issues are just as much economic as technical. Everyone agreed that this all comes about from the fact that we are no longer getting scaling from our litho platform, and we've been stuck on 193i for seven generations. Paul said that he thought the big issue was resistance, in particular liner resistance in contacts/vias, which doesn't scale. But unidirectional patterning means that even a little connection from one transistor to another has to go through several vias, making the problem worse. So one challenge is to lower the liner resistance, or thin it, or perhaps even have barrierless integration. The audience wondered if anything could be learned from 3D Flash memory. Anton pointed out that there are two game changers there. One is going 3D. But the other is MLC (multi-level cells). There were talks at IEDM about how to embed a memory device in a transistor so that it has four states—that could be a game changer but would also mean that we have to redo every standard cell. Craig said that 3D in general is a challenge since every customer wants something different, so that each solution is pretty much a one-off. That makes it hard for a foundry like GLOBALFOUNDRIES to make money since the volume is not there. David said that 3D could obviously solve the footprint problem, getting a lot of devices on a smaller die, but it was unlikely to do anything to solve the cost problem. Somehow the conversation moved to airgap. Chih-Chien said that there isn't a strong pull for airgap yet, but that foundries like UMC need to be ready and do the research. People speculated on whether airgap is a game-changer. After all, so far Intel is the only manufacturer using it. Craig reckoned that it was a "field of dreams" scenario and if we build it they will come. But is the only dielectric advantage for five or six generations. One problem is that you have to design to it and, since it costs more, you need to get something back to justify that. Everyone agreed that the big issue in BEOL was resistance. The big issue is the resistance in the liner inside contacts since all the current has to flow through it at the bottom of the contact hole. There is a showdown going on between Rubidium and Cobalt, and the dream is a strategy that is liner free. That gives three positives: lower resistance due to area, no liner at the bottom, and better material. At the end of the panel, I asked whether the resistance of the liner at the bottom of the contact was the biggest issue of all in BEOL and everyone agreed it was. Cobalt is not a solution since it doesn't stick, maybe Rubidium will save us, the search goes on. Lurking in the back of every discussion on process is EUV. Does it affect the BEOL if it does materialize? David said that it has immediate effect, first in the cut masks where three layers can be replaced with one. For vias, four layers can be replaced with one. Craig (of GLOBABLFOUNDRIES) said that it is not ready yet but getting there. Another issue is that when we go to the next node at 5nm then even with EUV we will need multiple patterning, and once you need SADP with EUV The cost benefit may go away. David said that there are two components of EUV cost saving. The obvious one is knocking mask passes out. But another is that if you plan for EUV then you can develop 2D design rules that leverage the patterning fidelity, and so get better density (plus avoid a lot of via resistance). Craig emphasized that if EUV can do 2D on the low levels of metal, then we can remove a lot of masks and have a much less complex process. Ed asked his last question: how far can copper be extended? Anton said it is all about 5nm and what we end up with there. At a certain line width, copper starts to be less attractive and there is a crossover. This is also tied up with the EUV question. But at some point Cobalt wins and Ruthenium maybe starts to win. Anton said it would be a mix. Most metal will be copper but the self-aligned stuff on the first couple of levels may not be copper, but m3 up will be. Someone in the audience pointed out that if you are a large microprocessor company then you can design your own m1/m2 and design cobalt, but foundry customers don't want to give up on copper. Craig agreed and said that if you are IBM you can optimize for this but across the board for foundry customers it is very difficult since you have to design for it. A final area for discussion was monolithic 3D. Everyone agreed that 3D packaging was not a game changer but nobody seems to know about integrated 3D. David went out on a limb and said "integrated 3D is the path for the future as 3D NAND has shown us". ARM had done some basic evaluations putting designs onto two tiers and could get a 20% power reduction with a monolithic/coolcube approach. But having copper interconnect on both tiers is a problem, ARM just assumed it even though nobody knows how to manufacture that. With that, we all vanished into the night. Previous: Dolby Atmos and Tensilica![]()
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