SPIE is the international society for optics and photonics, with the purpose of “advancing an interdisciplinary approach to the science and application of light”. What everyone calls "spie", however, is actually the SPIE Advanced Lithography Conference . The name SPIE doesn't stand for anything anymore; originally it had something to do with photography when it was founded back in 1955 (obviously pre-integrated circuit—maybe lithography still used stones?). In the semiconductor world, lithography (and, of course, silicon photonics) is the area of greatest interest. It is held at the San Jose Convention Center, 26 February through 2 March. Meanwhile, up the road, DVCon is taking place in the DoubleTree, but I'll cover what Cadence is doing there separately. Plenary Session Keynotes The plenary sessions at the conference take place on Monday morning, starting at 8:30am at the convention center. There are three: Frank Abboud, VP and GM of Intel's mask operations, on Photomask Challenges for Upcoming Technology Nodes Ben Tsai, KLA-Tencor's CTO, on Inspection and Metrology to Support the Quest for Perfection: Photolithography for the Sub-10nm nodes Nobu Koshiba, CEO of JSR on Materials Innovation: It's No Longer Only About Resolution EUV Keynotes Two other keynotes I think are must-see for many people are immediately after the plenary sessions, from 11am to 12pm in the EUV sub-conference : EUVL Readiness for High Volume Manufacturing , a keynote by Britt Turkot of Intel Progress in EUV lithography towards manufacturing , a keynote by Seong-Sue Kim of Samsung The biggest question in lithography, to my mind, is when EUV will be ready for high-volume manufacturing, and where it makes sense to use it. It is not just the light source and the photoresist, but do the pellicles work, progress toward defect-free masks, and so on. I used to be a skeptic that the technology would work at all, but ASML and their partners have made a lot of progress and although nobody has it in HVM yet, they have run a lot of wafers. Invited Papers Cadence is also presenting two invited papers with our partners imec and AMD, respectively. Listed below are the details, including the abstracts. Session 1: Keynote , Design-Process-Technology Co-Optimization for Manufacturability : Low track height standard-cells enable high-placement density and low-BEOL cost in N5 (Invited Paper); Marriott, San Jose Salon III, 8:40am – 10:00am Making standards cells smaller by lowering the cell height from 7.5 tracks to 6 tracks for the same set of ground rules is an efficient way to reduce the area for high-density digital IP blocks without increasing wafer cost. Denser cells however also imply a higher pin density and possible more routing congestion because of that. In Place and Route phase, this limits the cell density (a.k.a. utilization) that can be reached without design rule violations. This study shows that 6-track cells (192nm high) and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. With imec, paper 10148-2 Session 2: Physical Design Analytics and Machine Learning : Pattern-based analytics to estimate and track yield risk of designs down to 7nm (Invited Paper); Marriott, San Jose Salon III – 10:30am – 12:10pm At advanced technology nodes, physical design verification with patterns is essential to co-optimize design and process for improved yields. This work continues the effort to establish a methodology for full chip high-performance topological pattern analysis and the applications of this methodology towards analyzing design styles. This includes the study of variations and coverage of design space by patterns across technology nodes down to 7nm. Tracking patterns across different designs and process technology nodes using a database and defining key 'patterns of interest' (POI) will be discussed. With AMD, paper 10148-4 Other Cadence Papers: Tuesday, 28 February Optical Microlithography , Session 2: Pushing Optical Limits : In-design and signoff lithography physical analysis for 7nm/5nm, paper 10147-4; Convention Center 210C: 10:30am – 12:00pm Metrology, Inspection, and Process Control for Microlithography , Session Posters : A pattern-based method to automate mask inspection files , paper 10145-102; Convention Center Hall 2: 6:00pm – 8:00pm Other Cadence Papers: Wednesday, 1 March Optical Microlithography Session 6: Computation Lithography I : Full-chip hierarchical inverse lithography: A solution with perfect symmetry , paper 10147-20; Convention Center 210C: 10:40am – 12:20pm Session Posters : Advanced application of pattern-aware OPC , paper 10147-70; Convention Center Hall 2: 6:00pm – 8:00pm Design-Process-Technology Co-optimization for Manufacturability Session Posters , San Jose Convention Center Hall 2: 6:00 – 8:00pm Low-track height standard-cell design in N5 using scaling boosters , paper 10148-32 A fast process development by applying design technology co-optimization , paper 10148-42 Process weakness assessment by profiling all incoming design components , paper 10148-48 Using design differentiating methods to find suspect design patterns which cause failure , paper 10148-51 Electrical failure debug using interlayer profiling method , paper 10148-52 Pattern database applications from design to manufacturing , paper 10148-54 Other Cadence Papers: Thursday, 2 March Session 5: Design-Process-Technology-Co-optimization : Exploiting regularity: breakthroughs in sub-7nm place-and-route (Invited Paper), paper 10148-14; Marriott, San Jose Salon III: 8:00 – 10:10am Session 6: Design Interactions with Metrology: Joint Session with Conferences 10148 and 10145 : A pattern-based design analysis method by using inline inspection data more efficiently , paper 10148-21; Convention Center 220B: 10:40am – 12:00pm Session 8: Methodologies for Design-Process-Technology-Co-optimization : Transforming information from silicon testing and design characterization into numerical data sets for yield learning , paper 10148-31; Convention Center 220C: 3:40 – 5:20 pm Exhibition and More Details Cadence is exhibiting at booth #325. Hours are Tuesday 2/28 from 10-5 and Wednesday 3/1 from 10-4. For full details of these papers, including the authors and abstracts, go to the conference website . To register for the conference (note that prices increase 10 February) go here .![]()
![]()
↧