One of the first posts I wrote here at Breakfast Bytes was Where Does 5 Really Mean 30? about process node naming. One company that is heavily involved with process nodes is ASML, and they have attempted to standardize nomenclature to a "standard node". In a paper at the 31st European Mask and Lithography Conference, Gerald Dicker, Diederik de Bruin, Brennan Peterson, Pieter Wöltgens, Boudewijn Sluijk, and Peter Jenkins (all from ASML) published a paper titled Getting Ready for EUV in HVM . I didn't attend the conference, but I did download the paper. Thanks to Scotten Jones of IC Knowledge for first telling me about this and pointing me at the paper. There are two separate shrink roadmaps, DRAM, and logic. (There used to be three but flash will continue to "shrink" for the foreseeable future by going vertical and backing off being so aggressive on the basic process dimensions. DRAM For DRAM, of course, the most important dimension is the size of the bit cell, the area occupied by one bit. The area for the drivers is not zero but the die size is dominated by the volume of bit cells. These have been tracking for 0.842 per year, and squaring that gets to 50% per two years, which corresponds to Moore's Law. Since something like 98% of all transistors is actually memory, this is very important, in terms of process learning. The graph below shows how it has tracked, although there are challenges in DRAM to keeping on the line going forward. Logic For logic, roadmaps have followed the two year beat of Moore's Law since the integrated circuit was invented. One of the most amazing things about Moore's Law is that he formulated it with just a 5 data points when an IC held just 64 transistors. Today they hold...er...more. For logic, more information is revealed by looking at the metal half-pitch and the gate half-pitch. The number of metal tracks gives the height of standard cells, and the poly pitch gives the length (depending on how many transistors are required to implement the functionality). The poly pitch is usually referred to as the contacted poly half pitch (CPHP) since that is actually the limitation in practice. The metal is known as the minimum metal half pitch (MMHP). The graph below shows how the product of those two factors ties into the "conventional" node name. ASML's standard node uses the formula to get the numbers to line up: 0.14 * (CPHP * MMHP) 0.67 They don't say explicitly, but I think the weird numbers have been chosen to line up on Intel's naming, which is actually less aggressive than the foundries, perhaps because there is little advantage to Intel in using a "marketing" name for the process. Their customers just want better processors and don't care much what the name of the process in which they were manufactured was. But the formula can be applied to any process and it removes that brinkmanship. I'm not going to run the numbers, I'll leave that as an exercise for the reader. EUV Insertion The rest of the paper is looking at an analysis of where EUV will be cost effective going forward. But since the paper was presented in 2015, the data is out of date. If you want the up to date picture from two of ASML's customers, and if you are going the SPIE Advanced Lithography Conference in a few weeks, then I recommend the two keynotes of the EUV track: EUVL Readiness for High Volume Manufacturing , a keynote by Britt Turkot of Intel Progress in EUV lithography towards manufacturing , a keynote by Sue Kim of Samsung If you want to read the paper, you can download it here (it will cost you $18).![]()
![]()
↧