Cadence’s Sigrity team speaks to a lot of power integrity tool users. Experts in both DC analysis and AC analysis are constantly collaborating with us. A couple of years ago, a group of engineers from Cisco came to our CDNLive event in Silicon Valley and presented an idea. Team Sigrity listened and heard all the nice things they had to say about tools like Sigrity ™ PowerDC™ and Sigrity ™ OptimizePI™ , but there was a clearly received message … “Make it easier!” You can read that paper here . The message was received. We understood that the PI expert needs some help. We understood that information entered in the schematic could and should be saved to make the power integrity analysis setup automated. We understood that when components are used on multiple designs, source, sink, electrical constraints and target impedance profiles should be saved in a library for re-use. And we understood that if the setup was automated, the PI expert could then share the analysis responsibility with other members of the team. We got it. Message received. So, it took a few meetings. And it took a couple of rounds of prototypes. And it took a few beta customers. But now, with the Sigrity 2017 release that was announced at DesignCon 2017 , power integrity analysis really is made much easier. In combination with the Sigrity portfolio release, the DesignCon 2017 proceedings will include the paper: Team-Based PCB PDN Design Methodology Enabled by IC Target Impedance Constraints where you can hear from two of Team Sigrity about the process of performing AC analysis by applying the PowerTree™ data captured early in the design process and then applying Sigrity AC optimization schemes to correct a design problem where target impedance constraints were not being met. PowerTree data contains target impedance constraints Use the Decap optimization workflow to meet the target impedance constraint In the Cadence booth, we will have demonstration pod devoted to power integrity analysis. You can expect to see us demonstrating how the flow envisioned by Cisco has been realized in the latest release. We recently sat down with John Lin, Signal/Power Integrity Director, DCG in Lenovo and he gave us a user’s perspective on the tools and the Sigrity 2017 release . He said, “Using Cadence’s Sigrity SI/PI tools has allowed us to shorten development cycles and ensure good design quality. New features, such as the PowerTree technology, in the 2017 Sigrity portfolio will allow us to use the tools more efficiently. This continues a long history of Cadence building in improvements to EDA software that enable us to shorten our simulation times effectively.” If John’s user perspective doesn’t make you want to come by and see a demo at DesignCon, then you obviously cannot spell PI (^_^)! Just in case you cannot make it, here is a sneak peek at the PowerTree technology being used for DC analysis. Use PowerTree view to quickly cross probe to problem areas We hope you will want to learn more about the Sigrity 2017 release and how you can let your Power Integrity experts share some of that first order analysis burden with the PCB Design team. Together your design team and Team Sigrity hope to make 2017 a great year! Team Sigrity![]()
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