Paolo Gargini gave the opening keynote at GOMAC recently. It was titled The Secret of Success: Roadmap, Research, Prototyping, and Manufacturing . He has been involved in the direction of semiconductor technology for several decades. He has had two hats during that period, being an Intel fellow and Director of Technology Strategy, and at the same time he was the chairman of the International Technology Roadmap for Semiconductors (ITRS, and before that NTRS). That has now moved up a level and has been subsumed into the International Roadmap for Devices and Systems (IRDS), which he is currently chairman of (although he has retired from Intel). All of this has given him a ringside seat during the most dramatic exponential growth of any industry ever. With some justification, those roadmaps have been described as summarizing what it will take to keep Moore's Law true. Paolo pointed out that if you have enough notice, then in 15 years you can get a lot done. The first 10 years are academic and laboratory research, and then the volume manufacturers and the equipment vendors step in, perfect the technology so that it yields, and bring it to market. To do it any faster than this requires huge sums of money and usually doesn't work anyway. But with enough time, a lot of smart people will work out a lot of approaches and winnow it down to the winner. Given all the moving parts of the industry, from equipment to semiconductor manufacturers to materials, there can only really be one winner, since the entire industry needs to agree. Paolo put it succinctly: "Universities can work hard, work long, and are cheap. But everything takes 10 years. With more money you can put more people, more equipment, or more material, but you can't buy more time. But if you start early enough, time is free." I was reminded of this a year and a half ago at an IEDM short course on what 5nm would be like. In the morning, a lot of academics presented various interesting technologies that might be significant one day, such as TFETS and carbon nanotubes. Then a couple of industrial experts, if I remember right both from IBM, came and talked about what 5nm FEOL and BEOL would really be like. They pointed out that it took 10 years for ideas like FinFET and Damascene copper to go from academic success to high-volume manufacturing (HVM), perhaps Paolo's 15 years from when the research started. Based on those timeframes alone, the IBM experts said, the FEOL at 5nm would be very like FinFET, even gate-all-around might be pushing it, and the BEOL would be copper with, perhaps, some optimization in the contact liners. None of the academic ideas, promising as they might be, would be ready for HVM before about 2025, way past 5nm. Based on what we can now see, that seems a pretty accurate assessment. Paolo divided semiconductor scaling into three phases: 1975-2003: We had geometrical scaling, with Dennard scaling in effect so that we got more transistors, faster transistors, and the same power at each node. During this period we went from bipolar, to PMOS, to NMOS, to CMOS without breaking step. 2003-2021: This period has what he called equivalent scaling. Using techniques like strained silicon and FinFETs, we got something that looked close to geometric scaling although there were now a lot more moving parts. However, Dennard scaling was over and power was maxed out. 2021-2030+: Here he predicts what he calls 3D power scaling, when we will take the lessons of 3D NAND Flash and move them into logic. Dr. Moore, Meet Dr. Dennard During the early days of the semiconductor industry there were two fundamental scaling laws. The first was concerned with ways to increase the number of transistors in a cost-effective way, doubling every two years. Of course this is Moore's Law. The second law identified a way to improve transistor performance by geometric scaling and reducing the voltage. These were Dennard's guidelines, leading to faster transistors for the same power budget. A key point that Paolo emphasized is that even though the goals of these two laws were completely different, they initially shared the common element of scaling transistor dimensions. As a result, the two laws were linked (or confused) on the part of most people. In fact, the dimensional scaling was an essential part of Dennard scaling, but not of Moore's Law. For example, NAND flash is blazing the way in vertical scaling, accelerating Moore's Law, for that market segment anyway, without dimensional scaling. In fact, the opposite, since the process used for 3D NAND flash is less aggressive than the most advanced 2D NAND flash. Dennard scaling ended when power dissipation limits for MOS transistors were reached. The focus switched from increasing switching speed, the goal for the previous 40 or so years, to reducing switching energy for the same performance. This manifested itself at the system level as a plateauing of processor clock speeds, and a switch towards multi-core as delivering more aggregate performance. This worked well for some applications. It is not fundamentally hard to scale a datacenter to service 100,000 users with 100,000 cores. But speeding up most applications on the same hardware base is either impossible or unsolved, depending on your level of optimism. Any concurrent programming task runs into the wall of Amdahl's law. I won't go into the details, but basically there is a maximum speedup limited by how much of the task cannot be parallelized. In the limit, if, say, 5% cannot be parallelized then the maximum speedup is 20X, when those 100,000 cores run the parallelizable part essentially instantaneously, leaving just the 5% remaining out of the original 100%. Paolo's view is that Moore's Law has continued unabated for the last 50 years, since Gordon Moore first casually penned it in a widely unnoticed (at the time) article. It will continue for at least the next 10 to 15 years. Dennard scaling (for some reason nobody ever calls it a law) ended well over a decade ago. Paolo's colleague at Intel, Pat Gelsinger, famously pointed out that if we continued to push up clock rates despite not being in Dennard scaling any more, then microprocessors would have the same power density as a rocket nozzle, and that wasn't going to happen. And he wasn't even talking about smartphones in our pockets. Because Moore's Law and Dennard scaling were linked for so long, the slow progress in computing performance has been seen as the end of Moore's Law, while all the evidence is that it is continuing on its historical trend. Multicore is a symptom of Moore's Law continuing while Dennard scaling stopped, lots of transistors but only the same speed as before. Wafer Volume Even the most casual observer of the semiconductor industry, perhaps a Wall Street analyst (that was a snarky joke, by the way), knows that fabs get increasingly expensive. The current generation under construction seems to have a price tag of around $10B. In fact there is another "law" sometimes called Moore's Second Law, and sometimes called Rock's Law after the VC who funded Intel. This states that the cost of a fab doubles every four years. There is a reason for this. Moore's Law is about what the economically optimum number of transistors to put on a die is. That depends on a lot of factors, such as die size, transistor structure, and so on. But one other factor is wafer volume. The main reason that fabs get more expensive is not so much that they require more expensive equipment (though they do), but that the economic scale increases with each process generation, too. There needs to be a huge volume to amortize the huge cost (a modern fab depreciates at around $50 per second, depending on your assumptions). One joke in the semiconductor industry is that 7nm is for 7 companies, and 5nm is for 5 companies. But, in fact, there are only four companies that build leading-edge node (non-memory) fabs. Palo's old employer Intel, TSMC, Samsung, and GLOBALFOUNDRIES. The message that Paolo emphasized is that just talking about the cost reduction per transistor from one node to the next ignores a key ingredient: wafer volume. Research I said earlier that Paolo had the notion that if you work early with research institutions, and give them 10 years, they can come up with technology breakthroughs. Then companies like Intel can take those breakthroughs and commercialize them to HVM. He gave some examples through his career. He was involved in the start of Sematech, which at its peak had a $200M budget. One problem was that at Sematech everyone worried about enabling the competition. It was seen as a way of getting free government money to do the stuff they planned to do anyway (to be fair, the big European programs like ESPRIT were also seen as a way for the big European technology companies to get shoveled money by the governments with a veneer of respectability). Paolo got Intel involved with imec, at the time with just a tiny budget. But they had a secret: they could work on anything. By 2007, they had the real thing working: Hi-K metal gate. Sematech...not. Hi-K metal gate solved a huge scaling problem that had looked insurmountable. 3nm of Hafnium oxide avoided the problem of having to go to 1nm. A lot of other semiconductor companies started to work with imec and their budget went from $70M up to $250M. Another example was FinFET. Intel worked with UC Berkeley (Chenming Hu and his team) from the beginning. Everyone laughed at the idea at first. Two decades earlier, in 1998, Paolo had predicted that the end of MOS transistors would be metal gate-all-around (see the right hand part of the above diagram) although nobody knew how to build it and if it would work. FinFET has the gate on three sides of the channel (which is why Intel calls it tri-gate), so it is three-fourths of the way to GAA (although it is horizontal still). FinFET is actually another example of Moore's Law continuing without it just being linear scaling. Semiconductor companies get criticized for their process nomenclature. At 1um, the gate really was one micron across. Try and find anything that is 10nm across in a 10nm process. But there is a real sense in which it looks like a 1um process scaled to 10nm to the designer. Paolo (and others) call this equivalent scaling. The Future Paolo talked about a lot more than I can cover in one post that is already over long. He expects to see the lessons of 3D NAND Flash to be extended into logic, with Moore's law continuing by going vertical (at the die level, not just 3D packaging, which is already here, there's some in your phone already). This will involve heterogeneous integration of logic, memory, and other capabilities, in a single die (on a single wafer for manufacturing purposes). The third dimension really is different since we can deposit thin films much more accurately than we can do lithography, "but it will take industry another five years to come around and see that the work has already been done." As to transistors, in 2005 new research was initiated to find a new switch. By 2010, the tunnel FET (TFET) emerged as a real thing, initially combined with FinFET, but perhaps eventually on its own. Negative capacitance FET (NC FET) is also promising, at lower power than FinFET. Carbon nanotubes (CNT) continue to make progress and Paolo predicts they will "eventually be crowned as the new long-term switch" if the manufacturing issues can be solved. They are very attractive offering both lower power and higher performance than MOS. But Paolo cautioned that at some level he is not the expert. "I'm just the conductor, I don't claim to play any of the instruments." Read More (About Moore) In March, Paolo had an article on this topic published in IEEE's Computing in Science and Engineering titled How to Successfully Overcome Inflection Points, or Long Live Moore's Law . It is available for download from the IEEE website for somewhere between free and $33 depending on your status with IEEE. The IEEE has lots more information on the International Roadmap for Devices and Systems (IRDS). We have third-wave coffee shops now, this is the third generation of the semiconductor technology roadmap (NTRS, ITRS, IRDS).![]()
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