If you listen to presentations about high-speed networking for datacenters, you will hear a lot about retimers and gearboxes. With optical networks, one challenge is how you get from the optical domain to the electrical domain. After all, you can't just hook up an optical fiber to a pin on your SoC. This is done with some sort of photodetector, either a separate sensor component, or an on-chip silicon photonics detector. But there is another problem to be addressed. Whether on copper or fiber, the signals transmitted contain their own embedded clock. At the receiver, this clock is recovered. So you have data arriving with its own clock, and an SoC that also has its own clock. There are all the usual issues about synchronizing signals across clock domains, but there is a higher level issue, too. The clocking scheme used typically has two features. One is that, no matter what data is transmitted, signal transitions occur sufficiently often that a phased-lock loop (PLL) can be kept synchronized. The other is that DC balance is achieved, so that power is not wasted driving a DC component of the signal (over time, obviously) that carries no information. The simplest case to understand is the old Manchester encoding used by the original 10Mbps Ethernet (and the even more original PARC 3Mbps network) where 0 was represented by a half-bit 0 followed by a half-bit 1, and 1 was represented by a half-bit 1 followed by a half-bit 0. This meant that every bit contained a transition in the middle (there may be transitions on the bit boundaries, too) and obviously there is no DC component since everything is balanced at the bit level. Modern protocols balance over longer periods, since the speeds are too high to have only half a bit per sample, having as many as 2 bits per sample (PAM4, PAM standing for pulse-amplitude modulation). To handle the mismatch between the recovered clock and the SoC clock, a FIFO is introduced into the receiver. This adds some latency but reduces the jitter close to zero. However, over longer periods of time, the FIFO will either become full or empty since there is no guarantee that the mismatch between the two clocks will average out to zero. So over time, the incoming data may get several bits ahead of the receiver, or alternatively the receiver may be ready to clock some data but the fiber hasn't supplied it yet. This is handled by having fill words that are recognized at a pretty low level. If the receiver gets ahead of the SoC (so data is "piling up") then the next fill word can safely be discarded to get everything back together. If the receiver gets behind (so no data is available when it is required) then a fill word is generated while more data arrives. On the transmit side, fill words are added to the data stream regularly so that the receiver has something to delete if necessary. This approach keeps everything synchronized. The component (which may be an on-chip block) that does this is called a retimer. At some higher level, once everything is running synchronized to the SoC clock, all the dummy frames are ignored. A second problem is that the data rate on the fiber or copper might be higher than the raw data. For example, five nodes generating data at 10Gbps can be put down a single 50Gbps fiber. This is clearly attractive for one obvious reason, only one fiber instead of five. And one less obvious reason is that one limiting factor in the construction of modern datacenter networks is faceplate space, that only a certain number of sockets can fit across the width of a single rack for attachment of cables (whether copper or fiber). This approach requires signals to be merged together on the transmit side, and to be split apart on the receive side. The component that does this is called a gearbox. At the recent Linley Cloud Hardware Conference, there were a couple of interesting presentations by Scott Feller of Inphi and Chris Collins of Macom, who both supply chips into the high-performance datacenter networking space. Scott pointed out two secular trends, the transition from copper to fiber, and the move from analog-based signaling to more complex signal schemes such as PAM4 that require DSP processing. Scott emphasized something Andy pointed out in the keynote, the IEEE standardization process is too slow and so most of the heavy lifting is being done by MSAs, multi-source agreements, where the key players agree and build interoperable interfaces long before the standardization process is complete. Fiber has historically had higher data rates than copper, at least over very short distances. For example, 10G over fiber happened in 2001, but took until 2008 on copper; 25G was 2008 on fiber, but 2013 on copper. Scott sees 2017 as the year of the interception, where the two roadmaps merge, with 50G available on both optical and electrical at the same time, using PAM4. The expected 200G and 400G adoptions will drive the transition to PAM even harder. Scott's conclusions: Market transition to PAM is gaining momentum PAM volumes growing as switches with 50G PAM I/O sample Shift to optical and DSP-based equalization 200G and 400G adoptions will accelerate the transition to PAM Chris showed how the pressure to increase lane rates is relentless, driven by the fact that faceplate size remains constant but the faceplate throughput has to be the same as the switch capacity. With 100G per lane, you get 32x400G per faceplate. To make this work, power per bit needs to be reduced, and cost per bit needs to be reduced, which drives more bits per symbol and thus to PAM4, with two bits per symbol. Chris showed how 100G (and subsequently 200G and 400G) attack the space challenge, the thermal challenge and the cost challenge. Power is down by 1/3, component count by 2/3, plus lots of other positives like reduced assembly cost. One change is the transition from analog to digital, since at 16nm a digital implementation is more cost effective (not to mention being less demanding on the semiconductor manufacturing, test, and difficulty of design). Of course you still need ADCs and DACs, but everything else is handled digitally. Beyond 16nm (to 10nm, 7nm...infinity and beyond), the digital approach continues to scale whereas the analog approach either doesn't scale at all or does so only minimally. His summary: Bandwidth demand requires 100Gb/s DSP is attractive for both technical and commercial reasons, not to mention it scales for the future 100G/lane will enable 800G modules by 2018 Apart from the company names, Chris and Scott could have swapped their final slides.![]()
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