A design application can include a clock generation and distribution circuit where matching the exact propagation delay for the digital clock through the distribution circuit is the measurement goal. The sensitivity parameters to include are The length of the transmission lines The RLC components within the circuit The propagation delay variables within the design. The feedback and compensation circuits of the clock buffers. Once the sensitive components are identified utilizing the sensitivity analysis, you can utilize the optimizer to match the exact parameters to meet the measurement goal. A histogram of the propagation delay can be generated by utilizing the Monte Carlo feature of PSpice Advanced Analysis. Determining the characteristics of the clocking distribution circuit is critical in terms of meeting specifications for clock and data setup and hold times, this analysis can be conducted with PSpice Advanced Analysis. Post-Layout Analysis The post-Layout analysis can be conducted with SigXplorer within the Allegro Sigrity SI toolkit. Image is shown for a specific net. Pre-Layout Analysis However the initial analysis is required at the schematic level so that accurate information is provided in the constraint manager database before routing is initiated. This initial analysis can be conducted with PSpice Advanced Analysis in terms of what the propagation delay should be for the transmission lines. For more information go to PSpice.com![]()
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