The basic rule of thumb in terms of high speed design guidelines includes taking into account the parasitics of the transmission path/ channel link. With PSpice Advanced Analysis the capacitive parasitic effect of single ended traces can be included in the transient simulation.To showcase the impact of parasitic capacitance lets zoom in on a subset of a larger and complex design, and modify the subset of the design to a simple operational amplifier design: On executing a transient analysis the output of the design is shown: The measurement values are the maximum and minimum values of Vout. In order to improve the accuracy of the design the sensitivity analysis feature of PSpice Advanced Analysis can be utilized. Note the parasitic capacitance is included in the analysis. The ideal output voltage needs to be +/1.5v, on executing the optimizer the values of the resistors and parasitic capacitors can be modified in the design. Note the optimizer also includes the parasitic capacitance. Modified the op-amp design with the feedback resistor values and parasitic capacitance values provided by the optimizer. The transient analysis provides the results Hence keeping the parasitic capacitance under check is critical to high speed designs. The 1pF on the feedback resistor network might be unrealistic, however the simulation provides the following data: If you utilize a high input impedance FET probe, proceed with caution when probing sensitive circuits. Remember to reduce the ground loops. In terms of routing, the trace length and trace capacitance need to be minimized. Precision resistors need to be utilized in the feedback circuits. Avoid transitioning layers on feedback circuits since this would introduce via inductance. Reference high speed design guidelines for more information and reference the articles, tutorials and demos available on PSpice.com![]()
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